ICX412_ データシートの表示（PDF） - Sony Semiconductor

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ICX412_

Timing Generator and Signal Processor for Frame Readout CCD Image Sensor

Sony Semiconductor 

CXD3412GA

Control data: D32 FGOB [Wide CLPOB generation]

This controls wide CLPOB generation during the vertical OPB period. See the Timing Charts for the actual

operation. The default is "OFF".

D32

Description of operation

0 Wide CLPOB generation OFF

1 Wide CLPOB generation ON

Control data: D34 , D35 PTOB [CLPOB waveform pattern]

This indicates the CLPOB waveform pattern. The default is "Normal".

D35 D34

0

0

0

1

1

0

1

1

Waveform pattern

(Normal)

(Shifted rearward)

(Shifted forward)

(Wide)

Control data: D36 , D37 LDAD [ADCLK logic phase]

This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO.

D37 D36 Degree of adjustment (°)

0

0

0

0

1

90

1

0

180

1

1

270

Control data: D38 , D39 STB [Standby]

The operating mode is switched as follows. However, the standby bits are loaded to the CXD3412GA and

control is applied immediately at the rising edge of SEN1.

D39 D38 Symbol

Operating mode

X

0 CAM Normal operating mode

0

1 SLP Sleep mode

1

1 STB Standby mode

See the Pin Status Table for the pin status in each mode.

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