ICX412_ データシートの表示（PDF） - Sony Semiconductor

部品番号

コンポーネント説明

メーカー

ICX412_

Timing Generator and Signal Processor for Frame Readout CCD Image Sensor

Sony Semiconductor 

Chart-3 Vertical Direction Timing Chart

MODE

AF1 mode

Applicable CCD image sensor

• ICX412

VD

HD

SUB

V1A

V1B

V2

V3A

V3B

V4

CCD OUT

PBLK

CLPOB

Wide CLPOB

CLPDM

ID/EXP

WEN

131

144 2

14

High-speed

E sweep block

D

E Frame shift block

6

4

131

144 2

14

High-speed

E sweep block

D

E Frame shift block

6

4

∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.

∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.

∗ 75 stages are fixed for high-speed sweep block; 68 stages are fixed for frame shift block.

∗ VD of this chart is NTSC equivalent pattern (142H + 1384ck + 1383ck units). For PAL equivalent pattern, it is 171H + 1296ck units.

High-speed sweep block starts from 159H.

Share Link: