CY7C0430BV-133BGI(2006) データシートの表示（PDF） - Cypress Semiconductor
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CY7C0430BV-133BGI Datasheet PDF : 37 Pages
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CY7C0430BV
CY7C0430CV
Switching Characteristics Over the Industrial Operating Range (continued)[6]
Parameter
Description
tCKLZ[9]
Clock HIGH to Output Low-Z
tSINT
Clock to INT Set Time
tRINT
Clock to INT Reset Time
tSCINT
Clock to CNTINT Set Time
tRCINT
Clock to CNTINT Reset Time
Master Reset Timing
tRS
Master Reset Pulse Width
tRSR
Master Reset Recovery Time
tROF
Master Reset to Output Flags Reset Time
Port to Port Delays
tCCS[6]
Clock to Clock Set-up Time (time required after a write
before you can read the same address location)
CY7C0430BV and CY7C0430CV
–133
–100
Min.
Max.
Min.
Max.
1
1
1
7.5
1
10
1
7.5
1
10
1
7.5
1
10
1
7.5
1
10
7.5
10
7.5
10
6.5
8
6.5
9
JTAG Timing and Switching Waveforms
Parameter
fJTAG
tTCYC
tTH
tTL
tTMSS
tTMSH
tTDIS
tTDIH
tTDOV
tTDOX
fBIST
tBH
tBL
Description
Maximum JTAG TAP Controller Frequency
TCK Clock Cycle Time
TCK Clock High Time
TCK Clock Low Time
TMS Set-up to TCK Clock Rise
TMS Hold After TCK Clock Rise
TDI Set-up to TCK Clock Rise
TDI Hold after TCK Clock Rise
TCK Clock Low to TDO Valid
TCK Clock Low to TDO Invalid
Maximum CLKBIST Frequency
CLKBIST High Time
CLKBIST Low Time
Quadport DSE Family
–133/–100
Min.
Max.
10
100
40
40
20
20
20
20
20
0
50
6
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
Document #: 38-06027 Rev. *B
Page 11 of 37
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