LHF32K10 データシートの表示（PDF） - Sharp Electronics

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LHF32K10

Flash Memory 32M (4MB × 8 / 2M × 16)

Sharp Electronics 

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LHF32K10

8

3 BUS OPERATION

The local CPU reads and writes flash memory in-

system. All bus cycles to or from the flash memory

conform to standard microprocessor bus cycles.

3.1 Read

Information can be read from any block, identifier

codes, query structure, or status register independent

of the VPP voltage. RP# must be at VIH.

The first task is to write the appropriate read mode

command (Read Array, Read Identifier Codes, Query

or Read Status Register) to the CUI. Upon initial

device power-up or after exit from deep power-down

mode, the device automatically resets to read array

mode. Five control pins dictate the data flow in and

out of the component: CE# (CE0#, CE1#), OE#, WE#,

RP# and WP#. CE0#, CE1# and OE# must be driven

active to obtain data at the outputs. CE0#, CE1# is

the device selection control, and when active enables

the selected memory device. OE# is the data output

(DQ0-DQ15) control and when active drives the

selected memory data onto the I/O bus. WE# and

RP# must be at VIH. Figure 17, 18 illustrates a read

cycle.

3.2 Output Disable

With OE# at a logic-high level (VIH), the device

outputs are disabled. Output pins DQ0-DQ15 are

placed in a high-impedance state.

3.3 Standby

Either CE0# or CE1# at a logic-high level (VIH) places

the device in standby mode which substantially

reduces device power consumption. DQ0-DQ15

outputs are placed in a high-impedance state

independent of OE#. If deselected during block

erase, full chip erase, (multi) word/byte write and

block lock-bit configuration, the device continues

functioning, and consuming active power until the

operation completes.

3.4 Deep Power-Down

RP# at VIL initiates the deep power-down mode.

In read modes, RP#-low deselects the memory,

places output drivers in a high-impedance state and

turns off all internal circuits. RP# must be held low for

a minimum of 100 ns. Time tPHQV is required after

return from power-down until initial memory access

outputs are valid. After this wake-up interval, normal

operation is restored. The CUI is reset to read array

mode and status register is set to 80H.

During block erase, full chip erase, (multi) word/byte

write or block lock-bit configuration modes, RP#-low

will abort the operation. STS remains low until the

reset operation is complete. Memory contents being

altered are no longer valid; the data may be partially

erased or written. Time tPHWL is required after RP#

goes to logic-high (VIH) before another command can

be written.

As with any automated device, it is important to

assert RP# during system reset. When the system

comes out of reset, it expects to read from the flash

memory. Automated flash memories provide status

information when accessed during block erase, full

chip erase, (multi) word/byte write and block lock-bit

configuration. If a CPU reset occurs with no flash

memory reset, proper CPU initialization may not

occur because the flash memory may be providing

status information instead of array data. SHARP’s

flash memories allow proper CPU initialization

following a system reset through the use of the RP#

input. In this application, RP# is controlled by the

same RESET# signal that resets the system CPU.

Rev. 1.55

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