IDT49C460 データシートの表示（PDF） - Integrated Device Technology

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IDT49C460

32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

Integrated Device Technology 

IDT49C460/A/B/C/D/E

32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS (Cont’d.)

Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

VLC = 0.2V; VHC = VCC – 0.2V

Symbol

Parameter

Test Conditions

Min. Typ. Max. Unit

ICCQ Quiescent Power Supply Current VCC = Max.; All Inputs

—

3.0

10 mA

(CMOS Inputs)

VHC ≤ VIN, VIN ≤ VLC

fOP = 0; Outputs Disabled

ICCT Quiescent Input Power Supply

VCC = Max., VIN = 3.4V, fOP = 0

Current (per Input @ TTL High) (5)

—

0.3

0.75 mA/

Input

ICCD Dynamic Power Supply Current VCC = Max.

MIL.

—

6

10 mA/

VHC ≤ VIN, VIN ≤ VLC

Outputs Open, OE = L

ICC

Total Power Supply Current (6)

VCC = Max., fOP = 10MHz

Outputs Open, OE = L

COM'L.

—

MIL.

—

COM'L.

—

6

7 MHz

60

110 mA

60

80

50 % Duty cycle

VHC ≤ VIN, VIN ≤ VLC

VCC = Max., fOP = 10MHz

Outputs Open, OE = L

MIL.

—

COM'L.

—

70

125

70

95

50 % Duty cycle

VIH = 3.4V, VIL = 0.4V

NOTES:

2584 tbl 27

5. ICCT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out ICCQ, then dividing by the total number of inputs.

6. Total Supply Current is the sum of the Quiescent current and the Dynamic current (at either CMOS or TTL input levels). For all conditions, the Total Supply

Current can be calculated by using the following equation:

ICC = ICCQ + ICCT (NT x DH) + ICCD (fOP)

DH = Data duty cycle TTL high period (VIN = 3.4V).

NT = Number of dynamic inputs driven at TTL levels.

fOP = Operating frequency in Megahertz.

CMOS TESTING CONSIDERATIONS

Special test board considerations must be taken into

account when applying high-speed CMOS products to the

automatic test environment. Large output currents are being

switched in very short periods and proper testing demands

that test set-ups have minimized inductance and guaranteed

zero voltage grounds. The techniques listed below will assist

the user in obtaining accurate testing results:

1) All input pins should be connected to a voltage potential

during testing. If left floating, the device may oscillate,

causing improper device operation and possible latchup.

2) Placement and value of decoupling capacitors is critical.

Each physical set-up has different electrical

characteristics and it is recommended that various

decoupling capacitor sizes be experimented with.

Capacitors should be positioned using the minimum lead

lengths. They should also be distributed to decouple

power supply lines and be placed as close as possible to

the DUT power pins.

3) Device grounding is extremely critical for proper device

testing. The use of multi-layer performance boards with

radial decoupling between power and ground planes is

necessary. The ground plane must be sustained from the

performance board to the DUT interface board and wiring

unused interconnect pins to the ground plane is

recommended. Heavy gauge stranded wire should be

used for power wiring, with twisted pairs being

recommended for minimized inductance.

4) To guarantee data sheet compliance, the input thresholds

should be tested per input pin in a static environment. To

allow for testing and hardware-induced noise, IDT

recommends using VIL ≤ 0V and VIH ≥ 3V for AC tests.

11.6

17

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