IDT72421L15(1995) データシートの表示（PDF） - Integrated Device Technology

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IDT72421L15
(Rev.:1995)

CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9

Integrated Device Technology 

IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

RCLK

tCLKH

tCLK

tCLKL

REN1,

REN2

EF

tENS

tENH

tREF

NO OPERATION

tA

Q0 - Q8

OE

WCLK

tOLZ

tOE

VALID DATA

tOHZ

tSKEW1 (1)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

tREF

WEN1

WEN2

2655 drw 08

NOTE:

1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between

the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge. Figure 6. Read Cycle

Timing

Figure 6. Read Cycle Timing

5.07

11

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