INTEL386 データシートの表示（PDF） - Intel

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INTEL386

Intel386 SX MICROPROCESSOR

Intel 

Intel386TM SX MICROPROCESSOR

The Intel386 SX Microprocessor has the ability to

handle up to 256 different interrupts exceptions In

order to service the interrupts a table with up to 256

interrupt vectors must be defined The interrupt vec-

tors are simply pointers to the appropriate interrupt

service routine In Real Mode the vectors are 4-byte

quantities a Code Segment plus a 16-bit offset in

Protected Mode the interrupt vectors are 8 byte

quantities which are put in an Interrupt Descriptor

Table Of the 256 possible interrupts 32 are re-

served for use by Intel and the remaining 224 are

free to be used by the system designer

INTERRUPT PROCESSING

When an interrupt occurs the following actions hap-

pen First the current program address and Flags

are saved on the stack to allow resumption of the

interrupted program Next an 8-bit vector is supplied

to the Intel386 SX Microprocessor which identifies

the appropriate entry in the interrupt table The table

contains the starting address of the interrupt service

routine Then the user supplied interrupt service

routine is executed Finally when an IRET instruc-

tion is executed the old processor state is restored

and program execution resumes at the appropriate

instruction

The 8-bit interrupt vector is supplied to the Intel386

SX Microprocessor in several different ways excep-

tions supply the interrupt vector internally software

INT instructions contain or imply the vector maska-

ble hardware interrupts supply the 8-bit vector via

the interrupt acknowledge bus sequence Non-

Maskable hardware interrupts are assigned to inter-

rupt vector 2

Maskable Interrupt

Maskable interrupts are the most common way to

respond to asynchronous external hardware events

A hardware interrupt occurs when the INTR is pulled

HIGH and the Interrupt Flag bit (IF) is enabled The

processor only responds to interrupts between in-

structions (string instructions have an ‘interrupt win-

dow‘ between memory moves which allows inter-

rupts during long string moves) When an interrupt

occurs the processor reads an 8-bit vector supplied

by the hardware which identifies the source of the

interrupt (one of 224 user defined interrupts)

Interrupts through interrupt gates automatically reset

IF disabling INTR requests Interrupts through Trap

Gates leave the state of the IF bit unchanged Inter-

rupts through a Task Gate change the IF bit accord-

ing to the image of the EFLAGs register in the task’s

Task State Segment (TSS) When an IRET instruc-

tion is executed the original state of the IF bit is

restored

Non-Maskable Interrupt

Non-maskable interrupts provide a method of servic-

ing very high priority interrupts When the NMI input

is pulled HIGH it causes an interrupt with an internal-

ly supplied vector value of 2 Unlike a normal hard-

ware interrupt no interrupt acknowledgment se-

quence is performed for an NMI

While executing the NMI servicing procedure the In-

tel386 SX Microprocessor will not service any further

NMI request or INT requests until an interrupt return

(IRET) instruction is executed or the processor is

reset If NMI occurs while currently servicing an NMI

its presence will be saved for servicing after execut-

ing the first IRET instruction The IF bit is cleared at

the beginning of an NMI interrupt to inhibit further

INTR interrupts

Software Interrupts

A third type of interrupt exception for the Intel386

SX Microprocessor is the software interrupt An INT

n instruction causes the processor to execute the

interrupt service routine pointed to by the nth vector

in the interrupt table

A special case of the two byte software interrupt INT

n is the one byte INT 3 or breakpoint interrupt By

inserting this one byte instruction in a program the

user can set breakpoints in his program as a debug-

ging tool

A final type of software interrupt is the single step

interrupt It is discussed in Single Step Trap

18

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