INTEL386 データシートの表示（PDF） - Intel

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INTEL386

Intel386 SX MICROPROCESSOR

Intel 

Intel386TM SX MICROPROCESSOR

Table 2 8 Register Values after Reset

Flag Word (EFLAGS)

Machine Status Word (CR0)

Instruction Pointer (EIP)

Code Segment (CS)

Data Segment (DS)

Stack Segment (SS)

Extra Segment (ES)

Extra Segment (FS)

Extra Segment (GS)

EAX register

EDX register

All other registers

uuuu0002H

uuuuuu10H

0000FFF0H

F000H

0000H

0000H

0000H

0000H

0000H

0000H

component and stepping ID

undefined

Note 1

Note 2

Note 3

Note 3

Note 4

Note 5

Note 6

NOTES

1 EFLAG Register The upper 14 bits of the EFLAGS register are undefined all defined flag bits are zero

2 The Code Segment Register (CS) will have its Base Address set to 0FFFF0000H and Limit set to 0FFFFH

3 The Data and Extra Segment Registers (DS ES) will have their Base Address set to 000000000H and Limit set to

0FFFFH

4 If self-test is selected the EAX register should contain a 0 value If a value of 0 is not found then the self-test has

detected a flaw in the part

5 EDX register always holds component and stepping identifier

6 All undefined bits are Intel Reserved and should not be used

DOUBLE FAULT

A Double Fault (exception 8) results when the proc-

essor attempts to invoke an exception service rou-

tine for the segment exceptions (10 11 12 or 13)

but in the process of doing so detects an exception

other than a Page Fault (exception 14)

RESET forces the Intel386 SX Microprocessor to

terminate all execution and local bus activity No in-

struction execution or bus activity will occur as long

as Reset is active Between 350 and 450 CLK2 peri-

ods after Reset becomes inactive the Intel386 SX

Microprocessor will start executing instructions at

the top of physical memory

One other cause of generating a Double Fault is the

Intel386 SX Microprocessor detecting any other ex-

ception when it is attempting to invoke the Page

Fault (exception 14) service routine (for example if a

Page Fault is detected when the Intel386 SX Micro-

processor attempts to invoke the Page Fault service

routine) Of course in any functional system not

only in Intel386 SX Microprocessor-based systems

the entire page fault service routine must remain

‘present‘ in memory

2 8 Reset and Initialization

When the processor is initialized or Reset the regis-

ters have the values shown in Table 2 8 The In-

tel386 SX Microprocessor will then start executing

instructions near the top of physical memory at lo-

cation 0FFFFF0H When the first Intersegment

Jump or Call is executed address lines A20 – A23 will

drop LOW for CS-relative memory cycles and the

Intel386 SX Microprocessor will only execute in-

structions in the lower one megabyte of physical

memory This allows the system designer to use a

shadow ROM at the top of physical memory to ini-

tialize the system and take care of Resets

2 9 Testability

The Intel386 SX Microprocessor like the Intel386

Microprocessor offers testability features which in-

clude a self-test and direct access to the page trans-

lation cache

SELF-TEST

The Intel386 SX Microprocessor has the capability

to perform a self-test The self-test checks the func-

tion of all of the Control ROM and most of the non-

random logic of the part Approximately one-half of

the Intel386 SX Microprocessor can be tested during

self-test

Self-Test is initiated on the Intel386 SX Microproces-

sor when the RESET pin transitions from HIGH to

LOW and the BUSY pin is LOW The self-test

takes about 220 clocks or approximately 33 millisec-

onds with a 16 MHz Intel386 SX CPU At the com-

pletion of self-test the processor performs reset and

begins normal operation The part has successfully

passed self-test if the contents of the EAX are zero

If the results of the EAX are not zero then the self-

test has detected a flaw in the part

20

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