INTEL386 データシートの表示（PDF） - Intel

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INTEL386

Intel386 SX MICROPROCESSOR

Intel 

Intel386TM SX MICROPROCESSOR

INTERRUPT AND EXCEPTION PRIORITIES

Interrupts are externally generated events Maska-

ble Interrupts (on the INTR input) and Non-Maskable

Interrupts (on the NMI input) are recognized at in-

struction boundaries When NMI and maskable

INTR are both recognized at the same instruction

boundary the Intel386 SX Microprocessor invokes

the NMI service routine first If maskable interrupts

are still enabled after the NMI service routine has

been invoked then the Intel386 SX Microprocessor

will invoke the appropriate interrupt service routine

As the Intel386 SX Microprocessor executes instruc-

tions it follows a consistent cycle in checking for

exceptions as shown in Table 2 6 This cycle is re-

peated as each instruction is executed and occurs

in parallel with instruction decoding and execution

INSTRUCTION RESTART

The Intel386 SX Microprocessor fully supports re-

starting all instructions after Faults If an exception is

detected in the instruction to be executed (exception

categories 4 through 10 in Table 2 6) the Intel386

SX Microprocessor invokes the appropriate excep-

tion service routine The Intel386 SX Microprocessor

is in a state that permits restart of the instruction for

all cases but those given in Table 2 7 Note that all

such cases will be avoided by a properly designed

operating system

Table 2 6 Sequence of Exception Checking

Consider the case of the Intel386 SX Microprocessor having just completed an instruction It then performs

the following checks before reaching the point where the next instruction is completed

1 Check for Exception 1 Traps from the instruction just completed (single-step via Trap Flag or Data

Breakpoints set in the Debug Registers)

2 Check for external NMI and INTR

3 Check for Exception 1 Faults in the next instruction (Instruction Execution Breakpoint set in the Debug

Registers for the next instruction)

4 Check for Segmentation Faults that prevented fetching the entire next instruction (exceptions 11 or 13)

5 Check for Page Faults that prevented fetching the entire next instruction (exception 14)

6 Check for Faults decoding the next instruction (exception 6 if illegal opcode exception 6 if in Real Mode

or in Virtual 8086 Mode and attempting to execute an instruction for Protected Mode only or exception

13 if instruction is longer than 15 bytes or privilege violation in Protected Mode (i e not at IOPL or at

CPLe0)

7 If WAIT opcode check if TSe1 and MPe1 (exception 7 if both are 1)

8 If ESCape opcode for numeric coprocessor check if EMe1 or TSe1 (exception 7 if either are 1)

9 If WAIT opcode or ESCape opcode for numeric coprocessor check ERROR input signal (exception 16

if ERROR input is asserted)

10 Check in the following order for each memory reference required by the instruction

a Check for Segmentation Faults that prevent transferring the entire memory quantity (exceptions 11

12 13)

b Check for Page Faults that prevent transferring the entire memory quantity (exception 14)

NOTE

Segmentation exceptions are generated before paging exceptions

Table 2 7 Conditions Preventing Instruction Restart

1 An instruction causes a task switch to a task whose Task State Segment is partially ‘not present‘ (An

entirely ‘not present‘ TSS is restartable) Partially present TSS’s can be avoided either by keeping the

TSS’s of such tasks present in memory or by aligning TSS segments to reside entirely within a single 4K

page (for TSS segments of 4K bytes or less)

2 A coprocessor operand wraps around the top of a 64K-byte segment or a 4G-byte segment and spans

three pages and the page holding the middle portion of the operand is ‘not present‘ This condition can

be avoided by starting at a page boundary any segments containing coprocessor operands if the

segments are approximately 64K-200 bytes or larger (i e large enough for wraparound of the coproces-

sor operand to possibly occur)

Note that these conditions are avoided by using the operating system designs mentioned in this table

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