M58CR032C100ZB6T データシートの表示（PDF） - STMicroelectronics

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M58CR032C100ZB6T

32 Mbit (2Mb x 16, Dual Bank, Burst ) 1.8V Supply Flash Memory

STMicroelectronics 

M58CR032C, M58CR032D

BUS OPERATIONS

There are two types of bus operations that control

the device: Asynchronous (Read, Page Read,

Write, Output Disable, Standby, Automatic Stand-

by and Reset/Power-Down) and Synchronous

(Synchronous Read and Synchronous Burst

Read).

The Dual Bank architecture of the M58CR032 al-

lows read/write operations in Bank A, while read

operations are being executed in Bank B or vice

versa. Write operations are only allowed in one

bank at a time (see Table 7).

See Table 3, Bus Operations, for a summary. Typ-

ically glitches of less than 5ns on Chip Enable or

Write Enable are ignored by the memory and do

not affect bus operations.

Asynchronous Read. Asynchronous Read oper-

ations read from the Memory Array, or specific

registers (Electronic Signature, Status Register,

CFI, Block Protection Status, Read Configuration

Register status and Protection Register) in the

Command Interface.

A valid Asynchronous Bus Read operation in-

volves setting the desired address on the Address

Inputs, applying a Low signal, VIL, to Chip Enable

and Output Enable and keeping Write Enable

High, VIH. The address is latched on the rising

edge of the Latch, L, input. The Data Inputs/Out-

puts will output the value, see Figure 11, Asyn-

chronous Read AC Waveforms, and Table 21,

Asynchronous Read AC Characteristics, for de-

tails of when the output becomes valid.

According to the device configuration the following

Read operations: Electronic Signature, Status

Register, CFI, Block Protection Status, Burst Con-

figuration Register Status and Protection Register

must be accessed as asynchronous read or as

single synchronous read.

Asynchronous Page Read. Asynchronous

Page Read operations can be used to read the

content of the memory array, where data is inter-

nally read and stored in a page buffer. The page

has a size of 4 words and is addressed by A0 and

A1 address inputs.

Valid bus operations are the same as Asynchro-

nous Bus Read operations but with different tim-

ings. The first read operation within the page has

identical timings, subsequent reads within the

same page have much shorter access times. If the

page changes then the normal, longer timings ap-

ply again. See Figure 12, Asynchronous Page

Read AC Waveforms and Table 21, Asynchro-

nous Read AC Characteristics for details on when

the outputs become valid.

Asynchronous Page Read is the default state of

the device when exiting power-down or after pow-

er-up.

Asynchronous Write. Bus Write operations are

used to write to the Command Interface of the

memory or latch Input Data to be programmed. A

valid Bus Write operation begins by setting the de-

sired address on the Address Inputs and setting

Chip Enable, E, and Write Enable, W, to VIL and

Output Enable to VIH. Addresses are latched on

the rising edge of L, W or E whichever occur first.

Commands and Input Data are latched on the ris-

ing edge of W or E whichever occurs first. Output

Enable must remain High, VIH, during the whole

Bus Write operation. See Figures 14 and 15, Write

AC Waveforms, and Tables 23 and 24, Write AC

Characteristics, for details of the timing require-

ments.

Write operations are asynchronous and the clock

is ignored during write.

Output Disable. The data outputs are high im-

pedance when the Output Enable, G, and Write

Enable, W, are High, VIH.

Standby. When Chip Enable is High, VIH, and the

Program/Erase Controller is idle, the memory en-

ters Standby mode and the Data Inputs/Outputs

pins are placed in the high impedance state, inde-

pendent of Output Enable, G, or Write Enable, W.

For the Standby current level see Table 19, DC

Characteristics.

Reset/Power-Down. The memory is in Power-

Down when the Burst Configuration Register is set

for Power-Down and RP is at VIL. The power con-

sumption is reduced to the Power-Down level, and

Outputs are in high impedance, independent of

Chip Enable E, Output Enable G or Write Enable

W. The memory is in reset mode when the Burst

Configuration Register is set for Reset and RP is

at VIL. The power consumption is the same of the

standby and the outputs are in high impedance.

After a Reset/Power-Down the device defaults to

Asynchronous Page Read, the Status Register is

cleared and the Burst configuration register de-

faults to Asynchronous Page read.

Automatic Standby. If CMOS levels (VDD ±

0.2V) are used to drive the bus and the bus is in-

active for 150ns or more in Read mode, the mem-

ory enters Automatic Standby where the internal

Supply Current is reduced to the Standby Supply

Current, IDD2. The Data Inputs/Outputs will still

output data if a Bus Read operation is in progress.

The automatic standby feature is not available

when the device is configured for synchronous

burst mode.

Synchronous Single Read. Synchronous sin-

gle Reads can be used to read the Electronic Sig-

nature, Status Register, CFI, Block Protection

Status, Burst Configuration Register Status or

12/62

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