M58CR032C100ZB6T データシートの表示（PDF） - STMicroelectronics

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M58CR032C100ZB6T

32 Mbit (2Mb x 16, Dual Bank, Burst ) 1.8V Supply Flash Memory

STMicroelectronics 

M58CR032C, M58CR032D

gram/Erase Controller does it automatically before

erasing.

Two Bus Write cycles are required to issue the

command.

s The first bus cycle sets up the Erase command.

s The second latches the block address in the

internal state machine and starts the Program/

Erase Controller.

If the second bus cycle is not Write Erase Confirm

(D0h), Status Register bits b4 and b5 are set and

the command aborts. Erase aborts if Reset turns

to VIL. As data integrity cannot be guaranteed

when the Erase operation is aborted, the block

must be erased again.

Once the command is issued the device outputs

the Status Register data when any address within

the bank is read. At the end of the operation the

bank will remain in Read Status Register until a

Read command is issued.

During Erase operations the bank containing the

block being erased will only accept the Read Sta-

tus Register command and the Program/Erase

Suspend command, all other commands will be ig-

nored. Typical Erase times are given in Table 12,

Program, Erase Times and Program/Erase Endur-

ance Cycles.

See Appendix B, Figure 22, Block Erase Flowchart

and Pseudo Code, for a suggested flowchart for

using the Block Erase command.

Bank Erase Command

The Bank Erase command can be used to erase a

bank. It sets all the bits within the selected bank to

’1’. All previous data in the bank is lost. The Bank

Erase command will ignore any protected blocks

within the bank. If the bank is protected then the

Erase operation will abort, the data in the bank will

not be changed and the Status Register will output

the error.

Two Bus Write cycles are required to issue the

command.

s The first bus cycle sets up the Bank Erase

command.

s The second latches the bank address in the

internal state machine and starts the Program/

Erase Controller.

If the second bus cycle is not Write Bank Erase

Confirm (D0h), Status Register bits b4 and b5 are

set and the command aborts. Erase aborts if Re-

set turns to VIL. As data integrity cannot be guar-

anteed when the Erase operation is aborted, the

bank must be erased again.

Once the command is issued the device outputs

the Status Register data when any address within

the bank is read. At the end of the operation the

bank will remain in Read Status Register until a

Read command is issued.

During Erase operations the bank being erased

will only accept the Read Status Register com-

mand and the Program/Erase Suspend command,

all other commands will be ignored. Typical Erase

times are given in Table 12, Program, Erase

Times and Program/Erase Endurance Cycles.

Program Command

The memory array can be programmed word-by-

word. Only one bank can be programmed at any

one time. The other bank must be in Read mode

or Erase Suspend. Two bus write cycles are re-

quired to issue the Program Command.

s The first bus cycle sets up the Program

command.

s The second latches the Address and the Data to

be written and starts the Program/Erase

Controller.

After programming has started, Read operations

in the bank being programmed output the Status

Register content.

During Program operations the bank being pro-

grammed will only accept the Read Status Regis-

ter command and the Program/Erase Suspend

command. Typical Program times are given in Ta-

ble 12, Program, Erase Times and Program/Erase

Endurance Cycles.

Programming aborts if Reset goes to VIL. As data

integrity cannot be guaranteed when the program

operation is aborted, the block containing the

memory location must be erased and repro-

grammed.

See Appendix B, Figure 18, Program Flowchart

and Pseudo Code, for the flowchart for using the

Program command.

Double Word Program Command

This feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel. The two words must differ only for the

address A0. Only one bank can be programmed at

any one time. The other bank must be in Read

mode or Erase Suspend.

Programming should not be attempted when VPP

is not at VPPH. The command can be executed if

VPP is below VPPH but the result is not guaranteed.

Three bus write cycles are necessary to issue the

Double Word Program command.

s The first bus cycle sets up the Double Word

Program Command.

s The second bus cycle latches the Address and

the Data of the first word to be written.

s The third bus cycle latches the Address and the

Data of the second word to be written and starts

the Program/Erase Controller.

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