MACH230-18JI データシートの表示（PDF） - Lattice Semiconductor

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MACH230-18JI

High-Density EE CMOS Programmable Logic

Lattice Semiconductor 

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)

(continued)

Parameter

Symbol

Parameter Description

-15

Min Max

-20

Min Max Unit

tWIGL

Input Latch Gate Width LOW

6

8

ns

tPDLL

Input, I/O, or Feedback to Output Through Transparent

Input and Output Latches

19

24 ns

tAR

Asynchronous Reset to Registered or Latched Output

20

25 ns

tARW

Asynchronous Reset Width (Note 1)

15

20

ns

tARR

Asynchronous Reset Recovery Time (Note 1)

10

15

ns

tAP

Asynchronous Preset to Registered or Latched Output

20

25 ns

tAPW

Asynchronous Preset Width (Note 1)

15

20

ns

tAPR

Asynchronous Preset Recovery Time (Note 1)

10

15

ns

tEA

Input, I/O, or Feedback to Output Enable (Note 3)

15

20 ns

tER

Input, I/O, or Feedback to Output Disable (Note 3)

15

20 ns

Notes:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified

where frequency may be affected.

2. See Switching Test Circuit for test conditions.

3. Parameters measured with 32 outputs switching.

MACH230-15/20 (Com’l)

13

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