MACH230-18JI データシートの表示（PDF） - Lattice Semiconductor

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MACH230-18JI

High-Density EE CMOS Programmable Logic

Lattice Semiconductor 

SWITCHING WAVEFORMS

Input, I/O, or

Feedback

Combinatorial

Output

VT

tPD

VT

Combinatorial Output

14132I-8

Input, I/O,

or Feed-

back

Clock

Registered

Output

Input, I/O, or

VT

Feedback

tS

tH

VT

tCO

Gate

Latched

VT

Out

Registered Output

14132I-9

tPDL

VT

tSL tHL

VT

tGO

VT

14132I-10

Latched Output (MACH 2, 3, and 4)

Clock

tWH

tWL

Clock Width

14132I-11

Gate

VT

tGWS

14132I-12

Gate Width (MACH 2, 3, and 4)

Registered

Input

Input

Register

Clock

VT

tSIR

tHIR

VT

tICO

Registered

Input

Input

Register

Clock

VT

VT

Combinatorial

Output

Notes:

VT

14132I-13

Registered Input (MACH 2 and 4)

Output

Register

Clock

tICS

VT

14132I-14

Input Register to Output Register Setup

(MACH 2 and 4)

1. VT = 1.5 V.

2. Input pulse amplitude 0 V to 3.0 V.

3. Input rise and fall times 2 ns–4 ns typical.

20

MACH230-10/15/20

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