56F8165(2007) データシートの表示（PDF） - Freescale Semiconductor

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56F8165
(Rev.:2007)

16-bit Digital Signal Controllers

Freescale Semiconductor 

Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued)

Signal

Name

Pin No.

Type

State

During

Reset

Signal Description

RXD1

41

(GPIOD7)

Input

Input/

Output

Input,

pull-up

enabled

Receive Data — SCI1 receive data input

Port D GPIO — This GPIO pin can be individually programmed

as an input or output pin.

After reset, the default state is SCI input.

To deactivate the internal pull-up resistor, clear bit 7 in the

GPIOD_PUR register.

TCK

115

Schmitt

Input,

Test Clock Input — This input pin provides a gated clock to

Input

pulled low synchronize the test logic and shift serial data to the

internally JTAG/EOnCE port. The pin is connected internally to a pull-down

resistor.

TMS

116

Schmitt

Input,

Test Mode Select Input — This input pin is used to sequence the

Input

pulled high JTAG TAP controller’s state machine. It is sampled on the rising

internally edge of TCK and has an on-chip pull-up resistor.

To deactivate the internal pull-up resistor, set the JTAG bit in the

SIM_PUDR register.

Note: Always tie the TMS pin to VDD through a 2.2K resistor.

TDI

117

Schmitt

Input,

Test Data Input — This input pin provides a serial input data

Input

pulled high stream to the JTAG/EOnCE port. It is sampled on the rising edge

internally of TCK and has an on-chip pull-up resistor.

To deactivate the internal pull-up resistor, set the JTAG bit in the

SIM_PUDR register.

TDO

118

Output

In reset, Test Data Output — This tri-stateable output pin provides a serial

output is output data stream from the JTAG/EOnCE port. It is driven in the

disabled, shift-IR and shift-DR controller states, and changes on the falling

pull-up is edge of TCK.

enabled

56F8365 Technical Data, Rev. 7

24

Freescale Semiconductor

Preliminary

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