MCF5275LCVM133 データシートの表示（PDF） - Freescale Semiconductor

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MCF5275LCVM133

Integrated Microprocessor Family Hardware Specification

Freescale Semiconductor 

Preliminary Electrical Characteristics

8.7 Processor Bus Output Timing Specifications

Table 13 lists processor bus output timings.

Table 13. External Bus Output Timing Specifications

Name

Characteristic

Symbol

Min

Max

Unit

Control Outputs

B6a

CLKOUT high to chip selects (CS[7:0]) valid 1

B6b

CLKOUT high to byte enables (BS[3:2]) valid2

B6c

CLKOUT high to output enable (OE) valid3

B7

CLKOUT high to control output (BS[3:2], OE) invalid

B7a

CLKOUT high to chip selects invalid

tCHCV

tCHBV

tCHOV

tCHCOI

tCHCI

—

0.5tCYC + 5.5 ns

—

0.5tCYC + 5.5 ns

—

0.5tCYC + 5.5 ns

0.5tCYC + 1.0

—

ns

0.5tCYC + 1.0

—

ns

Address and Attribute Outputs

B8

CLKOUT high to address (A[23:0]) and control (TS,

tCHAV

—

TSIZ[1:0], TIP, R/W) valid

B9

CLKOUT high to address (A[23:0]) and control (TS,

tCHAI

1.0

TSIZ[1:0], TIP, R/W) invalid

9

ns

—

ns

Data Outputs

B11

CLKOUT high to data output (D[31:16]) valid

tCHDOV

—

B12

CLKOUT high to data output (D[31:16]) invalid

tCHDOI

1.0

B13

CLKOUT high to data output (D[31:16]) high impedance tCHDOZ

—

1 CS transitions after the falling edge of CLKOUT.

2 BS transitions after the falling edge of CLKOUT.

3 OE transitions after the falling edge of CLKOUT.

9

ns

—

ns

9

ns

Read/write bus timings listed in Table 13 are shown in Figure 8, Figure 9, and Figure 10.

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

25

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