MCF5275LCVM133 データシートの表示（PDF） - Freescale Semiconductor

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MCF5275LCVM133

Integrated Microprocessor Family Hardware Specification

Freescale Semiconductor 

Preliminary Electrical Characteristics

CLKOUT

CSn

B8

A[23:0]

TSIZ[1:0]

B8

TS

B8

TIP

OE

R/W (H)

BS[3:2]

D[31:16]

S0 S1 S2

S3

S4

S5

S0

S1

B6a

B7a

B9

B9

B6c

B9

B7

B6b

B7

TA (H)

B1a

TEA

B2a

Figure 10. SRAM Read Bus Cycle Terminated by TEA

8.8 DDR SDRAM AC Timing Characteristics

The DDR SDRAM controller uses SSTL2 and I/O drivers. Either Class I or Class II drive strength is

available and is user programmable. DDR Clock timing specifications are given in Table 14 and Figure 11.

Table 14. DDR Clock Timing Specifications1

Symbol

Characteristic

VMP

VOUT

VID

VIX

Clock output mid-point voltage

Clock output voltage level

Clock output differential voltage (peak to peak swing)

Clock crossing point voltage

Min

Max

Unit

1.05

1.45

V

-0.3

0.7

1.05

SDVDD + 0.3

V

SDVDD + 0.6

V

1.45

V

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

28

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

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