CY7C4231-25JC データシートの表示（PDF） - Cypress Semiconductor

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CY7C4231-25JC

64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

Cypress Semiconductor 

CY7C4421/4201/4211/4221

CY7C4231/4241/4251

Switching Waveforms (continued)

Programmable Almost Empty Flag Timing

tCLKH

tCLKL

WCLK

WEN1

tENS tENH

WEN2

(if applicable)

PAE

RCLK

REN1,

REN2

tENS tENH

tSKEW2 [18]

Note

19

tPAE

N + 1 WORDS

INFIFO

tENS

tENS tENH

Note

20

tPAE

42X1–12

Programmable Almost Full Flag Timing

tCLKH

tCLKL

WCLK

WEN1

tENS tENH

WEN2

(if applicable)

PAF

RCLK

tENS tENH

FULL − M+1 WORDS

IN FIFO

REN1,

REN2

Note

21

Note

22

tPAF

FULL − M WORDS

IN FIFO [23]

tSKEW2 [24]

tENS

tENS tENH

tPAF

42X1–13

Notes:

18. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the

rising RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.

19. PAE offset = n.

20. If a read is performed on this rising edge of the read clock, there will be Empty + (n – 1) words in the FIFO when PAE goes LOW.

21. If a write is performed on this rising edge of the write clock, there will be Full - (m – 1) words of the FIFO when PAF goes LOW.

22. PAF offset = m.

23. 64-m words for CY7C4421, 256 – m words in FIFO for CY7C4201, 512 – m words for CY7C4211, 1024 – m words for CY7C4221, 2048 – m words for

CY7C4231, 4096 – m words for CY7C4241, 8192 – m words for CY7C4251.

24. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK

and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.

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