PC8260 データシートの表示（PDF） - Atmel Corporation

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PC8260

PowerPC-based Communications Processors

Atmel Corporation 

PC8260 PowerQUICC II

Signal Descriptions

The PowerQUICC II system bus signals consist of all the lines that interface with the external bus. Many of these lines per-

form different functions, depending on how the user assigns them. Each signal’s pin number can be found in Table 4.

Table 4. External Signals

Pin

Signal Name

BR

60x Bus Request

BG

60x BusGrant

ABB

IRQ2

TS

60x Address Bus Busy

Interrupt Request 2

T-S 60x Bus Transfer Start

A[0:31]

60x Address Bus

TT[0:4]

TBST

TSIZ[0:3]

AACK

ARTRY

60x Bus Transfer Type

60x Bus Transfer Burst

60x Transfer Size

60x Address Acknowledge

60x Address Retry

Type

I/O

I/O

I/O

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Description

This is an output when an external arbiter is used and an input when an

internal arbiter is used. As an output, the PowerQUICC II asserts this pin

to request ownership of the 60x bus. As an input, an external master

should assert this pin to request 60x bus ownership from the internal

arbiter.

This is an output when an internal arbiter is used and an input when an

internal arbiter is used. As an output, the PowerQUICC II asserts this pin

to grant 60x bus ownership to an external bus master. As an input, an

external arbiter should assert this pin to grant 60x bus ownership to the

PowerQUICC II.

As an output the PowerQUICC II asserts this pin for the duration of the

address bus tenure. Following an AACK, which terminates the address

bus tenure, the PowerQUICC II negates ABB for a fraction of a bus cycle

and than stops driving this pin. As an input, the PowerQUICC II will not

assume 60x bus ownership, as long as it senses this pin is asserted by

an external 60x bus master.

This input is one of the eight external lines that can request (by means of

the internal interrupt controller) a service routine from the core.

Assertion of this pin signals the beginning of a new address bus tenure.

The PowerQUICC II asserts this signal when one of its internal 60x bus

masters (core, dma, PCI bridge) begins an address tenure. When the

PowerQUICC II senses this pin being asserted by an external 60x bus

master, it will respond to the address bus tenure as required (snoop if

enabled, access internal PowerQUICC II resources and memory

controller support).

When the PowerQUICC II is in the external master bus mode, these pins

function as the 60x address bus. The PowerQUICC II drives the address

of its internal 60x bus masters and will respond to addresses generated

by external 60x bus masters. When the PowerQUICC II is in the internal

master bus mode, these pins are used as address lines connected to

memory devices and controlled by the PowerQUICC II’s memory

controller.

The 60x bus master drives these pins during the address tenure to

specify the type of the transaction.

The 60x bus master asserts this pin to indicate that the current

transaction is a burst transaction (transfers 4 double words).

The 60x bus master drives these pins with a value indicating the amount

of bytes transferred in the current transaction.

A 60x bus slave asserts this signal to indicate that it has identified the

address tenure. Assertion of this signal terminates the address tenure.

Assertion of this signal indicates that the bus transaction should be

retried by the 60x bus master. The PowerQUICC II asserts this signal to

enforce data coherency with its internal cache and to prevent deadlock

situations.

21

2131B–HIREL–02/03

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