PC8260 データシートの表示（PDF） - Atmel Corporation

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PC8260

PowerPC-based Communications Processors

Atmel Corporation 

PC8260 PowerQUICC II

Table 4. External Signals (Continued)

Pin

Signal Name

L2 HIT

IRQ4

L2 Cache Hit

Interrupt Request 4

CPU BG

BADDR31

IRQ5

CPU BusGrant

Burst address 31

CPU DBG

CPU BR

CS[0:9]

CS[10]

BCTL1

DBG DIS

Interrupt Request 5

CPU Bus Data Bus Grant

CPU Bus Request

Chip Select

Chip Select

Buffer Control 1

Data Bus Grant Disable

CS[11]

AP[0]

Chip Select

Address Parity 0

BADDR[27:28] Burst Address 27:28

ALE

BCTLO

Address Latch Enable

Buffer Control 0

Type

I

I

O

O

I

O

O

O

O

O

O

O

I/O

O

O

Description

This pin is used for L2 cache control. Assertion of this pin indicates that

the 60x transaction will be handled by the L2 cache. In this case, the

memory controller will not start an access to the memory it controls.

This input is one of the eight external lines that can request (by means of

the internal interrupt controller) a service routine from the core.

The value of the60x core bus grant is driven on this pin for the

BADDR31 use of an external L2 cache. The driven bus grant is non

qualified. that is, in the IRQ5 case of external arbiter, the user should

qualify this signal with the bus grant input to the PowerQUICC II before

connecting it to the L2 Cache.

There are five burst address outputs of the 60x memory controller used

in the external master configuration and are connected directly to the

memory devices controlled by PowerQUICC II’s memory controller.

This input is one of the eight external lines that can request (by means of

the internal interrupt controller) a service routine from the core.

The value of the 60x core data bus grant is driven on this pin for the use

of an external L2 cache.

The value of the 60x core bus request is driven on this pin for the use of

an external L2 cache.

These are output pins that enable specific memory devices or

peripherals connected to PowerQUICC II buses.

This is an output pin that enables specific memory devices or

peripherals connected to PowerQUICC II buses.

Output signal whose function is to control buffers on the 60x data bus.

This pin will usually be used with BCTL0. The exact function of this pin is

defined by the value of SIUMCR[BCTLC]. See 6.5.1.8 SIU Module

Configuration Register for details.

This is an output when the PowerQUICC II is in external arbiter mode

and an input when the PowerQUICC II is in internal arbiter mode. When

this pin is asserted, the 60x bus arbiter should negate all of its DBG

outputs to prevent data bus contention.

Output that enables specific memory devices or peripherals connected

to PowerQUICC II buses.

The 60x master that drives the address bus, also drives the address

parity signals. The value driven on address parity 0 pin should provide

odd parity (odd number of 1’s) on the group of signals that includes

address parity 0 and A[0: 7].

There are five burst address output pins. These pins are outputs of the

60x memory controller. Used in external master configuration and

connected directly to the memory devices controlled by PowerQUICC

II’s memory controller.

This output pin controls the external address latch that should be used in

external master 60x bus configuration.

An Output whose function is to control buffers on the 60x data bus. This

pin will usually be used with BCTL1 that is MUXed on CS10. The exact

function of this pin is defined by the value of SIUMCR[BCTLC]. See

6.5.1.8 SIU Module Configuration Register for details.

25

2131B–HIREL–02/03

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