PC8260 データシートの表示（PDF） - Atmel Corporation

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PC8260

PowerPC-based Communications Processors

Atmel Corporation 

Table 4. External Signals (Continued)

Pin

Signal Name

L_A29

PCI_INTA

Local Bus Address 29

PCI INTA

L_A30

Local Bus Address 30

L_A31

DLLSYNC

LCL_D[0:31]

PCI_AD[0:31]

Local Bus Address 31

DLL Synchronization

Local Bus Data

PCI Address Data

LCL_DP[0:3]

PCI_C/BE[0:3]

Local Bus Data Parity

IRQ0

NMI_OUT

IRQ7

INT_OUT

APE

TRST

TCK

TMS

TDI

TDO

PCP Command/Byte

Enable

Interrupt request 0

Non Maskable Interrupt

Output

Interrupt Request 7

Interrupt Output

Address Parity Error

Test Reset (JTAG)

Test Clock (JTAG)

Test Mode Select (JTAG)

Test Data In (JTAG)

Test Data Out (JTAG)

Type

O

I/O

O

O

I

I/O

I/O

I/O

I/O

I

O

I

O

O

I

I

I

I

O

Description

In the local address bus, bit 14 is most significant and bit 31 is least

significant.

When the PowerQUICC II is the host in the PCI system, this pin is an

input for delivering PCI interrupts to the host. When the PowerQUICC II

is not the host of the PCI system, this pin is an output used by the

PowerQUICC II to signal an interrupt to the PCI host.

In the local address bus, bit 14 is most significant and bit 31 is least

significant.

In the local address bus, bit 14 is most significant and bit 31 is least

significant.

DLLSYNC is used to eliminate skew for the clock driven on CLKOUT.

In the local data bus, bit 0 is most significant and bit 31 is least

significant.

PCI bus address data input/output pins. In the PCI address data bus, bit

31 is most significant and bit 0 is least significant.

In local bus write operations the PowerQUICC II drives these pins. In

local bus read operations the accessed device drives these pins.

LCL_DP(0) is driven with a value that gives odd parity with LCL_D(0:7).

LCL-DP(1) is driven with a value that gives odd parity with LCL_D(8:15).

LCL_DP(2) is driven with a value that gives odd parity with

LCL_D(16:23).

LCL_DP(3) is driven with a value that gives odd parity with

LCL_D(24:31)

The PowerQUICC II drives these pins when it is the initiator of a PCI

transfer.

This input is one of the eight external lines that can request (by means of

the NMI-OUT internal interrupt controller) a service routine from the

core.

This is an output driven from PowerQUICC II’s internal interrupt

controller. Assertion of this output indicates that an unmasked interrupt

is pending in PowerQUICC II’s internal interrupt controller.

This input is one of the eight external lines that can request (by means of

the internal interrupt controller) a service routine from the core.

This is an output driven from PowerQUICC II’s internal interrupt

controller. Assertion of this output indicates that an unmasked interrupt

is pending in PowerQUICC II’s internal interrupt controller.

This output pin will be asserted when the PowerQUICC II’s detects

wrong parity driven on its address parity pins by an external master

This is the reset input to PowerQUICC II’s JTAG/COP controller.

This pin provides the clock input for PowerQUICC II’s JTAG/COP

controller.

This pin controls the state of PowerQUICC II’s JTAG/COP controller.

This pin is the data input to PowerQUICC II’s JTAG/COP controller.

This pin is the data output from PowerQUICC II’s JTAG/COP controller.

30 PC8260 PowerQUICC II

2131B–HIREL–02/03

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