PC8260 データシートの表示（PDF） - Atmel Corporation

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PC8260

PowerPC-based Communications Processors

Atmel Corporation 

PC8260 PowerQUICC II

Table 4. External Signals (Continued)

Pin

Signal Name

IRQ3

DP[3]

CKSTP OUT

EXT BR3

Interrupt Request 3

60x Data Parity 3

Checkstop Output

External Bus Request 3

IRQ4

DP[4]

CORE SRESET

EXT BG3

Interrupt Request 4

60x Data Parity 4

IRQ5

DP[5]

TBEN

EXT DBG3

Core system reset

External Bus Grant 3

Interrupt Request 5

60x Data Parity 5

IRQ6

DP[6]

CSE[0]

Time Base Enable

External Bus Grant3

Interrupt Request 6

60x Data Parity 6

IRQ7

DP[7]

CSE[1]

Cache Set Entry 0

Interrupt Request 7

60x Data Parity 7

Cache Set Entry 1

Type

I

I/O

O

I

I

I/O

I

O

I

I/O

I

O

I

I/O

O

I

I/O

O

Description

This input is one of the eight external lines that can request (by means of

the internal interrupt controller) a service routine from the core.

The 60x agent that drives the data bus, also drives the data parity

signals. The value driven on the data parity 3 pin should provide odd

parity (odd number of 1’s) on the group of signals that includes data

parity 3 and D[24:31].

Assertion of this pin indicates that the core is in its checkstop mode.

An external master should assert this pin to request 60x bus ownership

from the internal arbiter.

This input is one of the eight external lines that can request (by means of

the internal interrupt controller) a service routine from the core.

The 60x agent that drives the data bus, also drives the data parity

signals. The value driven on the data parity 4 pin should provide odd

parity (odd number of 1’s) on the group of signals that includes data

parity 4 and D[32:39].

Asserting this pin will force the core to branch to its reset vector.

The PowerQUICC II asserts this pin to grant 60x data bus ownership to

an external bus master.

This input is one of the eight external lines that can request (by means of

the internal interrupt controller) a service routine from the core.

The 60x agent that drives the data bus, also drives the data parity

signals. The value driven on the data parity 5 pin should provide odd

parity (odd number of 1’s) on the group of signals that includes data

parity 5 and D[40:47].

This is a count enable input to the Time Base counter in the core.

The PowerQUICC II asserts this pin to grant 60x data bus ownership to

an external bus master.

This input is one of the eight external lines that can request (by means of

the internal interrupt controller) a service routine from the core.

The 60x agent that drives the data bus, also drives the data parity

signals. The value driven on the data parity 6 pin should provide odd

parity (odd number of 1’s) on the group of signals that include data parity

6 and D[48:55].

The cache set entry outputs from the core, represent the cache

replacement set element for the current core transaction reloading into,

or writing out of, the cache.

This input is one of the eight external lines that can request (by means of

the internal interrupt controller) a service routine from the core.

The 60x master or slave that drives the data bus, also drives the data

parity signals. The value driven on the data parity 7pin should provide

odd parity (odd number of 1’s) on the group of signals that include data

parity 7 and D[56:63].

The cache set entry outputs from the core, represent the cache

replacement set element for the current core transaction reloading into,

or writing out of, the cache.

23

2131B–HIREL–02/03

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