HT9580 データシートの表示（PDF） - Holtek Semiconductor

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コンポーネント説明

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HT9580

Character Pager Controller

Holtek Semiconductor 

Preliminary

HT9580

(0005H). If the RTC counter is enabled, the

RTC counter will start to count. The RTC coun-

ter source clock is the X1-clock, so the X1 clock

setting via by SPF12, SPF13 and SPF14 should

be correct.

In order to guarantee that the system clock has

started and stabilized, the SST (System

Start-up Timer) provides an extra delay of 1024

system clock pulse when the system is powered

up.

1

0

RTC

Select 2Hz as the

RTC

Select 1Hz as the

RTC

The low power oscillator of the pager decoder

input clock should be crystal type. The decoder

subsystem low power oscillator, on the other

hand, is of a crystal type which is designed with

a power on start-up function to reduce the sta-

bilization time of the oscillator. This start-up

function is enabled by bit ²LPM² which is ini-

tially set high at power on reset, and should be

cleared to low so as to enable the low-power os-

cillator function. The oscillator configuration is

running in the low power mode.

The system clock oscillator can be enabled/dis-

abled by the register bit, ²HALT². The system

clock circuit is powered down, when the bit is

set to high. On the other hand, the system clock

V DD

100kW

50kW

50kW

100kW

LP M

( L o w p o w e r m o d e c o n tr o l)

X2

H T9580

X1

VSS

L o w p o w e r o s c illa to r fu n c tio n

low power oscillator

circuit is powered up, when the bit is low. When

this bit is set high, the CPU is also stopped.

When this bit is cleared low, the CPU core re-

turns to its normal operation. After this is set

HIGH by the software, it may also be cleared

low when reset, interrupt (IRQ or NMI), RTC

timeout, and port wake-up conditions are met.

0

1

HALT

System clock

enable

System clock

powered down

The WDT is a 16-bit counter and sourced by the

WDT-TMR (Watchdog timer) register

Address

0001H

0002H

Register

Name

WDT-TMR

CLR WDT

Bit 7

X

X

Bit 6

X

X

Bit 5

Bit 4

Bit 3

TMR0_PR1 TMR0_PR0 WDTEN

X

X

X

Bit 2

WS2

X

Bit 1

WS1

X

Bit 0

WS0

X

State on

POR

0000 0011

uuuu uuuu

sub-clock divided by 8. The counter is seg-

mented as a 9-bit prescaler and a 7-bit user pro-

grammable counter. The input clock is first

divided by 512 (9-stage) to get the nominal

time-out period. The output of the 9-bit

pre-scaler can then be divided by a 7-bit pro-

grammable counter to generate the longer

watchdog time-out depending on the user¢s re-

quirements. The 7-bit programmable counter is

controlled by 3 register bits, WS0~2. The

watchdog timer is enabled/disabled by a control

bit WDTEN. To prevent the overflow of this

watchdog timer, a clear-WDT operation should

be executed before the timer overflows. The

clear-WDT operation is to write any number to

the register, CLRWDT (0002H). When the

watchdog timer overflows (checked by bit 3 of

0006H ²WDTOVFG²), the program counter is

set to FFFC H and FFFD H to read the program

start vector. The definitions of the control bits

are listed below.

1

0

WDTEN

Enable the

watchdog timer

Disable the

watchdog timer

11

April 28, 2000

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