TFRA08C13 データシートの表示（PDF） - Agere -> LSI Corporation
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TFRA08C13 Datasheet PDF : 188 Pages
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TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet
October 2000
Pin Information (continued)
Table 2. Pin Descriptions (continued)
Pins
Symbol Type*
Description
A4
M1
W4
AE11
V23
M23
B20
C8
G23
RCHIDATAB[1]
RCHIDATAB[2]
RCHIDATAB[3]
RCHIDATAB[4]
RCHIDATAB[5]
RCHIDATAB[6]
RCHIDATAB[7]
RCHIDATAB[8]
LORLCK
I Receive CHI Data B. Serial input system data at 2.048 Mbits/s,
4.096 Mbits/s, or 8.192 Mbits/s.
O Loss of Receive Clock. This pin is asserted high (logic 1) when RLCK
in the receive framer does not toggle for a 250 µs interval. Once
asserted, this signal is deasserted on the first edge of RLCK (See Table
66. Global Control Register (GREG8) (008)).
H2
RLCK[1]
I Receive Framer Line Interface Clock. This is the 1.544 MHz DS1 or
U4
RLCK[2]
AF4
RLCK[3]
2.048 MHz input clock signal used by the receive framer to latch RPD
and RND data.
AF20
RLCK[4]
AF21
RLCK[5]
U24
RLCK[6]
G24
RLCK[7]
C13
RLCK[8]
B4
RPD[1]
I Receive Positive-Rail Data. NRZ serial data latched by the rising edge
K3
RPD[2]
W1
RPD[3]
of RLCK. Data rates: DS1-1.544 Mbits/s; CEPT-2.048 Mbits/s. Optional
single-rail NRZ receive data latched by the rising edge of RLCK.
AF10
RPD[4]
W24
RPD[5]
J26
RPD[6]
C20
RPD[7]
B5
RP81]
C6
RND[1]
I Receive Negative-Rail Data. Nonreturn-to-zero (NRZ) serial data
L2
RND[2]
W2
RND[3]
latched by the rising edge of RLCK. Data rates: DS1-1.544 Mbits/s;
CEPT-2.048 Mbits/s. In the single-rail mode, when RND = 1 the receive
bipolar violation counter increments once for each rising edge of RLCK.
AD9
RN[4]
V25
RND[5]
H25
RND[6]
B19
RND[7]
A5
RND[8]
* Iu indicates an internal pull-up, Id indicates an internal pull-down.
† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.
‡ Asserting this pin low will initially force RDY to a low state.
22
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