TFRA08C13 データシートの表示（PDF） - Agere -> LSI Corporation

部品番号

コンポーネント説明

メーカー

TFRA08C13

OCTAL T1/E1 Framer

Agere -> LSI Corporation 

Preliminary Data Sheet

October 2000

TFRA08C13 OCTAL T1/E1 Framer

Pin Information (continued)

Table 2. Pin Descriptions (continued)

Pins

Symbol Type*

Description

AD8

V26

AE10

INTERRUPT

RDY_DTACK

MPCK

O Interrupt. INTERRUPT is asserted high/low indicating an internal inter-

rupt condition/event has been generated. Interrupt events/conditions

are maskable through the control registers. This output can be wired-

OR or wired-AND to any other logic output (see Table 64Global Control

Register (GREG4) (004)).

O Ready. In the Intel interface mode, this pin is asserted high to indicate

the completion of a read or write access; this pin is forced into a high-

impedance state while CS is high.

Data Transfer Acknowledge (Active-Low). In the Motorola interface

mode, DTACK is asserted low to indicate the completion of a read or

write access; DTACK is 1 otherwise.

Iu Microprocessor Clock. Microprocessor clock used in the Intel mode to

generate the READY signal.

K1

TDO

O JTAG Data Output. Serial output data sampled on the falling edge of

TCK from the boundary-scan test circuitry.

J1

TDI

Iu JTAG Data Input. Serial input data sampled on the rising edge of TCK

for the boundary-scan test circuitry.

H3

TCK

Iu JTAG Clock Input. TCK provides the clock for the boundary-scan test

logic.

K2

TMS

Iu JTAG Mode Select (Active-High). The signal values received at TMS

are sampled on the rising edge of TCK and decoded by the boundary-

scan TAP controller to control boundary-scan test operations.

J2

TRST

Id JTAG Reset Input (Active-Low). Assert this pin low to asynchronously

initialize/reset the boundary-scan test logic.

* Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

‡ Asserting this pin low will initially force RDY to a low state.

LLuucceenntt TTeecchhnnoollooggiieess IInncc..

27

Share Link: