TFRA08C13 データシートの表示（PDF） - Agere -> LSI Corporation

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TFRA08C13

OCTAL T1/E1 Framer

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TFRA08C13 OCTAL T1/E1 Framer

Preliminary Data Sheet

October 2000

Pin Information (continued)

Table 2. Pin Descriptions (continued)

Pins

Symbol Type*

Description

V24

WR_DS

I Write (Active-Low). In the Intel mode, the value present on the data

bus is latched into the addressed register on the positive edge of the

signal applied to WR.

Data Strobe (Active-Low). In the Motorola mode, when AS is low and

R/W is low (write), the value present on the data bus is latched into the

addressed register on the positive edge of the signal applied to DS;

when AS is low and R/W is high (read), the TFRA08C13 drives the data

bus with the contents of the addressed register while DS is low.

U25

CS‡

I Chip Select (Active-Low). In the Intel interface mode, this pin must be

asserted low to initiate a read or write access and kept low for the dura-

tion of the access; asserting CS low forces RDY out of its high-imped-

ance state into a 0 state.

U23

ALE_AS

I Address Strobe (Active-Low). In the Motorola interface mode, this pin

must be asserted low to initiate a read or write access and kept low for

the duration of the access.

AD12

AE14

D0

I/O Microprocessor Data Bus. Bidirectional data bus used for read and

D1

write accesses. 3-stated output.

AC14

D2

AF14

D3

AD13

D4

AE15

D5

AF15

D6

AE16

D7

AC5

A0

I Microprocessor Address Bus. Address bus used to access the inter-

AD5

A1

nal registers.

AE6

A2

AC7

A3

AD6

A4

AF6

A5

AE7

A6

AF7

A7

AD7

A8

AE8

A9

AC9

A10

AF8

A11

* Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

‡ Asserting this pin low will initially force RDY to a low state.

26

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