UPD75008 データシートの表示（PDF） - NEC => Renesas Technology
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UPD75008 Datasheet PDF : 66 Pages
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µPD75004, 75006, 75008
3.2 NON PORT PINS
Also Served
Pin Name Input/Output As
Functon
TI0
PTO0
PCL
BUZ
SCK
SO/SB0
SI/SB1
Input
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
INT4
Input
INT0
INT1
Input
P13
Timer/event counter external event pulse Input
P20
Timer/event counter output
P22
Clock output
P23
Fixed frequency output (for buzzer or for trim-
ming the system clock)
P01
Serial clock input/output
Serial data output
P02
Serial bus input/output
Serial data input
P03
Serial bus input/output
Edge detection vector interrupt input (both
P00
rising and falling edge detection are effective)
P10
Edge detection vector
Clock synchronous
interrupt input (detection
P11
edge can be selected)
Asynchronous
When Reset
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input/
Output
Circuit
TYPE*1
B -C
E-B
E-B
E-B
F -A
F -B
M -C
B
B -C
INT2
Input
Edge detection testable
P12
input (rising edge detection) Asynchronous
Input
B -C
KR0-KR3
Input/
Output
P60-P63 Parallel falling edge detection testable input
Input
F -A
KR4-KR7
Input/
Output
P70-P73 Parallel falling edge detection testable input
Input
F -A
To connect the crystal/ceramic oscillator to the
main system clock generator. When inputting the
X1, X2
Input
—
external clock, input the external clock to pin X1,
Input
—
and the reverse phase of the external clock to pin
X2.
XT1
Input
To connect the crystal oscillator to the subsystem
clock generator.
Input
—
When the external clock is used, pin XT1 inputs
—
XT2
—
the external clock. In this case, pin XT2 must be
left open.
—
RESET
Input
—
System reset input
—
B
NC *2
—
—
No connection
—
—
VDD
—
—
Positive power supply
—
—
VSS
—
—
GND
—
—
*1: Circles indicate Schmitt trigger inputs.
2: When sharing the printed circut board with the µPD75P008, the NC pin must be directly
connected to VDD.
11
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