DS28E01-100 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS28E01-100 Datasheet PDF : 16 Pages
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Abridged Data Sheet
DS28E01-100
LEGACY VALUES
DS28E01-100 VALUES
PARAMETER
STANDARD SPEED OVERDRIVE SPEED STANDARD SPEED OVERDRIVE SPEED
tSLOT (incl. tREC)
tRSTL
tPDH
tPDL
tW0L
MIN
61µs
480µs
15µs
60µs
60µs
MAX
(undef.)
(undef.)
60µs
240µs
120µs
MIN
7µs
48µs
2µs
8µs
6µs
MAX
(undef.)
80µs
6µs
24µs
16µs
MIN
65µs1)
480µs
15µs
60µs
60µs
MAX
(undef.)
640µs
60µs
240µs
120µs
MIN
8µs1)
48µs
2µs
8µs
6µs
MAX
(undef.)
80µs
6µs
24µs
15.5µs
1) Intentional change, longer recovery time requirement due to modified 1-Wire front end.
PIN DESCRIPTION
NAME
FUNCTION
IO
1-Wire bus interface. Open drain, requires external pull-up resistor.
GND
Ground reference
NC
Not connected
DESCRIPTION
The DS28E01-100 combines 1024 bits of EEPROM organized as four 256-bit pages, a 64-bit secret, a register
page, a 512-bit SHA-1 engine, a 64-bit ROM registration number in a single chip. Data is transferred serially
through the 1-Wire protocol, which requires only a single data lead and a ground return. The DS28E01-100 has an
additional memory area called the scratchpad that acts as a buffer when writing to the memory, the register page,
or when installing a new secret. Data is first written to the scratchpad from where it can be read back. After the data
has been verified, a copy scratchpad command transfers the data to its final memory location, provided that the
DS28E01-100 receives a matching 160-bit MAC. The computation of the MAC involves the secret and additional
data stored in the DS28E01-100 including the device’s registration number. Only a new secret can be loaded
without providing a MAC. The SHA-1 engine is also activated to compute 160-bit MACs when performing an
authenticated read of a memory page and when computing a new secret, instead of loading it.
The DS28E01-100 understands a unique command "Refresh Scratchpad." Proper use of a refresh sequence after
a copy scratchpad operation reduces the number of weak bit failures if the device is used in a touch environment
(see the Writing with Verification section). The refresh sequence also provides a means to restore functionality in a
device with bits in a weak state.
The device's 64-bit ROM registration number guarantees unique identification and is used to address the device in
a multidrop 1-Wire network environment, where multiple devices reside on a common 1-Wire bus and operate
independently of each other. Applications of the DS28E01-100 include printer cartridge configuration and
monitoring, medical sensor authentication and calibration, and system intellectual property protection.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of the
DS28E01-100. The DS28E01-100 has six main data components: 1) 64-bit lasered ROM, 2) 64-bit scratchpad, 3)
four 256-bit pages of EEPROM, 4) register page, 5) 64-bit secrets memory, and 6) a 512-bit SHA-1 (Secure Hash
Algorithm) engine. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first
provide one of the seven ROM function commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM,
5) Resume Communication, 6) Overdrive-Skip ROM, or 7) Overdrive-Match ROM. Upon completion of an overdrive
ROM command byte executed at standard speed, the device enters overdrive mode where all subsequent commu-
nication occurs at a higher speed. The protocol required for these ROM function commands is described in Figure
10. After a ROM function command is successfully executed, the memory and SHA-1 functions become accessible
and the master can provide any one of the 9 available function commands. The function protocols are described in
Figure 8*. All data is read and written least significant bit first.
* For Figure 8 see the full version of the data sheet.
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