DS28E01-100 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS28E01-100

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

Dallas Semiconductor -> Maxim Integrated 

Abridged Data Sheet

DS28E01-100

TRANSACTION SEQUENCE

The protocol for accessing the DS28E01-100 through the 1-Wire port is as follows:

ƒ Initialization

ƒ ROM Function Command

ƒ Memory/SHA Function Command

ƒ Transaction/Data

INITIALIZATION

All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a

reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence

pulse lets the bus master know that the DS28E01-100 is on the bus and is ready to operate. For more details, see

the 1-Wire Signaling section.

1-Wire ROM FUNCTION COMMANDS

Once the bus master has detected a presence, it can issue one of the seven ROM function commands that the

DS28E01-100 supports. All ROM function commands are 8 bits long. A list of these commands follows (refer to the

flow chart in Figure 10).

READ ROM [33h]

This command allows the bus master to read the DS28E01-100’s 8-bit family code, unique 48-bit serial number,

and 8-bit CRC. This command can only be used if there is a single slave on the bus. If more than one slave is

present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a

wired-AND result). The resultant family code and 48-bit serial number result in a mismatch of the CRC.

MATCH ROM [55h]

The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific

DS28E01-100 on a multidrop bus. Only the DS28E01-100 that exactly matches the 64-bit ROM sequence,

including the external address, responds to the following Memory/Control Function command. All other slaves wait

for a reset pulse. This command can be used with a single or multiple devices on the bus.

SEARCH ROM [F0h]

When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or

their device ID numbers. By taking advantage of the wired-AND property of the bus, the master can use a process

of elimination to identify the device ID numbers of all slave devices. For each bit of the device ID number, starting

with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device

participating in the search outputs the true value of its device ID number bit. On the second slot, each slave device

participating in the search outputs the complemented value of its device ID number bit. On the third slot, the master

writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop

participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both

states of the bit. By choosing which state to write, the bus master branches in the ROM code tree. After one

complete pass, the bus master knows the device ID number of a single device. Additional passes identify the

device ID numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm for a detailed

discussion, including an example.

SKIP ROM [CCh]

This command can save time in a single-drop bus system by allowing the bus master to access the memory

functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a

read command is issued following the Skip ROM command, data collision occurs on the bus as multiple slaves

transmit simultaneously (open-drain pulldowns produce a wired-AND result).

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