FM4005 データシートの表示（PDF） - Ramtron International Corporation
部品番号
コンポーネント説明
メーカー
FM4005 Datasheet PDF : 23 Pages
| |||
FM4005
0Ch
RC
CC
C2P
C1P
0Bh
SNL
VBC
VTP1-0
Event Counter Control
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
RC
CC
C2P
C1P
Read Counter. Setting this bit to 1 takes a snapshot of the four counters bytes allowing the system to read the
values without missing count events. The RC bit will be automatically cleared.
Counter Cascade. When CC=0, the event counters operate independently according to the edge programmed by
C1P and C2P respectively. When CC=1, the counters are cascaded to create one 32-bit counter. The registers of
Counter 2 represent the most significant 16-bits of the counter and CNT1 is the controlling input. Bit C2P is not
used when CC=1. Battery-backed, read/write.
CNT2 detects falling edges when C2P = 0, rising edges when C2P = 1. C2P has no effect on counter operation
when CC=1. Battery-backed, read/write.
CNT1 detects falling edges when C1P = 0, rising edges when C1P = 1. Battery-backed, read/write.
Companion Control
D7
D6
D5
D4
D3
D2
D1
D0
SNL
-
-
-
-
VBC
VTP1
VTP0
Serial Number Lock. Setting to a 1 makes registers 11h to 18h and SNL permanently read-only. SNL cannot be
cleared once set to 1. Nonvolatile, read/write.
VBAK charger control. Setting VBC to 1 causes a 15 µA trickle charge current to be supplied on VBAK. Clearing
VBC to 0 disables the charge current. Nonvolatile, read/write.
VTP select. These bits control the reset trip point for the low VDD reset function. Nonvolatile, read/write.
VTP
VTP1 VTP0
2.6V
0
0
2.9V
0
1
3.9V
1
0
4.4V
1
1
0Ah
WDE
WDT4-0
Watchdog Control
D7
D6
D5
D4
D3
D2
D1
D0
WDE
-
-
WDT4
WDT3
WDT2
WDT1
WDT0
Watchdog Enable. When WDE=1 the watchdog timer can cause the /RST signal to go active. When WDE = 0 the
timer runs but has no effect on /RST. Note as the timer is free-running, users should restart the timer using WR3-0
prior to setting WDE=1. This assures a full watchdog timeout interval occurs. Nonvolatile, read/write.
Watchdog Timeout. Indicates the minimum watchdog timeout interval with 100 ms resolution. New watchdog
timeouts are loaded when the timer is restarted by writing the 1010b pattern to WR3-0. Nonvolatile, read/write.
09h
WTR
POR
Watchdog timeout
WDT4 WDT3 WDT2 WDT1 WDT0
Invalid – default 100 ms
0
0
0
0
0
100 ms
0
0
0
0
1
200 ms
0
0
0
1
0
300 ms
...
0
0
0
1
1
2000 ms
1
0
1
0
0
2100 ms
1
0
1
0
1
2200 ms
...
1
0
1
1
0
2900 ms
1
1
1
0
1
3000 ms
1
1
1
1
0
Disable count
1
1
1
1
1
Watchdog Restart & Flags
D7
D6
D5
D4
D3
D2
D1
D0
WTR
POR
LB
-
WR3
WR2
WR1
WR0
Watchdog Timer Reset Flag: When the /RST signal is activated by the watchdog the WTR bit will be set to 1. It
must be cleared by the user. Note that both WTR and POR could be set if both reset sources have occurred since
the flags were cleared by the user. Battery-backed. Read/Write (internally set, user can clear bit).
Power-on Reset Flag: When the /RST pin is activated by either VDD < VTP or a manual reset, the POR bit will be
Rev. 2.3
Oct. 2006
Page 12 of 23
Share Link: 