FM4005 データシートの表示（PDF） - Ramtron International Corporation
部品番号
コンポーネント説明
メーカー
FM4005 Datasheet PDF : 23 Pages
| |||
FM4005
Reserved
CALS
CAL.4-0
Reserved bits. Do not use. Should remain set to 0.
Calibration sign. Determines if the calibration adjustment is applied as an addition to or as a subtraction from the
time-base. Calibration is explained on page 7. Nonvolatile, read/write.
These five bits control the calibration of the clock. Nonvolatile, read/write.
00h
Flags/Control
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
CF
Reserved
Reserved
Reserved
CAL
W
R
CF
CAL
W
R
Reserved
Century Overflow Flag. This bit is set to a 1 when the values in the years register overflows from 99 to 00. This
indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. The user should record the new
century information as needed. This bit is cleared to 0 when the Flag register is read. It is read-only for the user.
Battery-backed, read/write.
Calibration Mode. When set to 1, the clock enters calibration mode. When CAL is set to 0, the clock operates
normally, and the CAL/PFO pin is controlled by the comparator. Battery-backed, read/write.
Write Time. Setting the W bit to 1 freezes the clock. The user can then write the timekeeping registers with
updated values. Resetting the W bit to 0 causes the contents of the time registers to be transferred to the
timekeeping counters and restarts the clock. Battery-backed, read/write.
Read Time. Setting the R bit to 1 copies a static image of the timekeeping core and place it into the user
registers. The user can then read them without concerns over changing values causing system errors. The R bit
going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior to reading again. Battery-
backed, read/write.
Reserved bits. Do not use. Should remain set to 0.
Two-wire Interface
The FM4005 employs an industry standard two-wire
bus that is familiar to many users. Since the FM4005
is a real-time clock and processor companion and not
a memory device, it is accessed using a unique Slave
Address (Slave ID = 1101b).
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is
controlling the bus is the master. The master is
responsible for generating the clock signal for all
operations. Any device on the bus that is being
controlled is a slave. The FM4005 is always a slave
device.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions:
Start, Stop, Data bit, and Acknowledge. The figure
below illustrates the signal conditions that specify
the four states. Detailed timing diagrams are shown
in the electrical specifications.
SCL
SDA
7
6
0
Stop
Start
(Master) (Master)
Data bits
(Transmitter)
Data bit Acknowledge
(Transmitter) (Receiver)
Figure 8. Data Transfer Protocol
Start Condition
A Start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All read and write transactions begin with a
Start condition. An operation in progress can be
aborted by asserting a Start condition at any time.
Aborting an operation using the Start condition will
ready the FM4005 for a new operation.
If the power supply drops below the specified VTP
during operation, any 2-wire transaction in progress
will be aborted and the system must issue a Start
condition prior to performing another operation.
Stop Condition
A Stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations must end with a Stop condition.
Rev. 2.3
Oct. 2006
Page 14 of 23
Share Link: 