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MACHLV210-24 データシートの表示(PDF) - Lattice Semiconductor
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コンポーネント説明
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MACHLV210-24
High Density EE CMOS Programmable Logic
Lattice Semiconductor
MACHLV210-24 Datasheet PDF : 29 Pages
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BLOCK DIAGRAM
I/O
0
–I/O
7
I/O Cells
8
Macrocells
8
8
8
Macrocells
OE
44 x 68
AND Logic Array
and
Logic Allocator
22
22
44 x 68
AND Logic Array
and
Logic Allocator
OE
Macrocells
88
I/O Cells
8
Macrocells
8
I/O
24
–I/O
31
I/O
8
–I/O
15
I/O Cells
8
Macrocells
8
8
8
Macrocells
OE
44 x 68
AND Logic Array
and
Logic Allocator
22
Switch Matrix
22
44 x 68
AND Logic Array
and
Logic Allocator
OE
Macrocells
88
I/O Cells
8
Macrocells
8
I
0
–I
1,
I
3
–I
4
2
4
2
2
I/O
16
–I/O
23
CLK
0
/I
2,
CLK
1
/I
5
17908D-1
2
MACHLV210-12/15/20
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