M80C286 データシートの表示（PDF） - Intel

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M80C286

HIGH PERFORMANCE CHMOS MICROPROCESSOR WITH MEMORY MANAGEMENT AND PROTECTION

Intel 

M80C286

from the tables in memory The 16-bit offset is add-

ed to the segment base address to form the physical

address as shown in Figure 10 The tables are auto-

matically referenced by the CPU whenever a seg-

ment register is loaded with a selector All M80C286

instructions which load a segment register will refer-

ence the memory based tables without additional

software The memory based tables contain 8 byte

values called descriptors

of control and task switching The M80C286 has

segment descriptors for code stack and data seg-

ments and system control descriptors for special

system data segments and control transfer opera-

tions see Figure 10 Descriptor accesses are per-

formed as locked bus operations to assure descrip-

tor integrity in multi-processor systems

CODE AND DATA SEGMENT DESCRIPTORS

(S e 1)

Besides segment base addresses code and data

descriptors contain other segment attributes includ-

ing segment size (1 to 64K bytes) access rights

(read only read write execute only and execute

read) and presence in memory (for virtual memory

systems) (See Figure 11) Any segment usage vio-

lating a segment attribute indicated by the segment

descriptor will prevent the memory cycle and cause

an exception or interrupt

271103 –8

Figure 9 Protected Mode Memory Addressing

DESCRIPTORS

Descriptors define the use of memory Special types

of descriptors also define new functions for transfer

Must be set to 0 for compatibility with 80386

271103 – 9

Figure 10 Code or Data Segment Descriptor

Type

Field

Definition

12

Bit

Position

7

6–5

4

3

2

1

3

2

1

0

Access Rights Byte Definition

Name

Function

Present (P)

Pe1

Pe0

Descriptor Privilege

Level (DPL)

Segment Descrip-

tor (S)

Se1

Se0

Segment is mapped into physical memory

No mapping to physical memory exits base and limit are

not used

Segment privilege attribute used in privilege tests

Code or Data (includes stacks) segment descriptor

System Segment Descriptor or Gate Descriptor

Executable (E)

Expansion Direc-

tion (ED)

Writeable (W)

Ee0

ED e 0

ED e 1

We0

We1

Data segment descriptor type is

Expand up segment offsets must be s limit

Expand down segment offsets must be l limit

Data segment may not be written into

Data segment may be written into

If

Data

Segment

* (S e 1

E e 0)

Executable (E)

Conforming (C)

Readable (R)

Ee1

Ce1

R e0

Re1

Code Segment Descriptor type is

Code segment may only be executed

when CPL tDPL and CPL

remains unchanged

Code segment may not be read

Code segment may be read

If

Code

Segment

* (S e 1

E e 1)

Accessed (A)

Ae0

Ae1

Segment has not been accessed

Segment selector has been loaded into segment register

or used by selector test instructions

Figure 11 Code and Data Segment Descriptor Formats

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