M80C286 データシートの表示（PDF） - Intel

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M80C286

HIGH PERFORMANCE CHMOS MICROPROCESSOR WITH MEMORY MANAGEMENT AND PROTECTION

Intel 

M80C286

Code and data (including stack data) are stored in

two types of segments code segments and data

segments Both types are identified and defined by

segment descriptors (S e 1) Code segments are

identified by the executable (E) bit set to 1 in the

descriptor access rights byte The access rights byte

of both code and data segment descriptor types

have three fields in common present (P) bit De-

scriptor Privilege Level (DPL) and accessed (A) bit

If P e 0 any attempted use of this segment will

cause a not-present exception DPL specifies the

privilege level of the segment descriptor DPL con-

trols when the descriptor may be used by a task

(refer to privilege discussion below) The A bit shows

whether the segment has been previously accessed

for usage profiling a necessity for virtual memory

systems The CPU will always set this bit when ac-

cessing the descriptor

Data segments (S e 1 E e 0) may be either read-

only or read-write as controlled by the W bit of the

access rights byte Read-only (W e 0) data seg-

ments may not be written into Data segments may

grow in two directions as determined by the Expan-

sion Direction (ED) bit upwards (ED e 0) for data

segments and downwards (ED e 1) for a segment

containing a stack The limit field for a data segment

descriptor is interpreted differently depending on the

ED bit (see Figure 11)

A code segment (S e 1 E e 1) may be execute-

only or execute read as determined by the Read-

able (R) bit Code segments may never be written

into and execute-only code segments (R e 0) may

not be read A code segment may also have an attri-

bute called conforming (C) A conforming code seg-

ment may be shared by programs that execute at

different privilege levels The DPL of a conforming

code segment defines the range of privilege levels

at which the segment may be executed (refer to priv-

ilege discussion below) The limit field identifies the

last byte of a code segment

SYSTEM SEGMENT DESCRIPTORS (S e 0

TYPE e 1 – 3)

In addition to code and data segment descriptors

the protected mode M80C286 defines System Seg-

ment Descriptors These descriptors define special

system data segments which contain a table of de-

scriptors (Local Descriptor Table Descriptor) or seg-

ments which contain the execution state of a task

(Task State Segment Descriptor)

Figure 12 gives the formats for the special system

data segment descriptors The descriptors contain a

24-bit base address of the segment and a 16-bit lim-

it The access byte defines the type of descriptor its

state and privilege level The descriptor contents are

valid and the segment is in physical memory if P e1

If P e 0 the segment is not valid The DPL field is

only used in Task State Segment descriptors and

indicates the privilege level at which the descriptor

may be used (see Privilege) Since the Local De-

scriptor Table descriptor may only be used by a spe-

cial privileged instruction the DPL field is not used

Bit 4 of the access byte is 0 to indicate that it is a

system control descriptor The type field specifies

the descriptor type as indicated in Figure 12

System Segment Descriptor

Must be set to 0 for compatibility with 80386

271103 – 10

System Segment Descriptor Fields

Name Value

Description

TYPE

1

Available Task State Segment (TSS)

2

Local Descriptor Table

3

Busy Task State Segment (TSS)

P

DPL

BASE

0

1

0–3

24-bit

number

Descriptor contents are not valid

Descriptor contents are valid

Descriptor Privilege Level

Base Address of special system data

segment in real memory

LIMIT 16-bit Offset of last byte in segment

number

Figure 12 System Segment Descriptor Format

GATE DESCRIPTORS (S e 0 TYPE e 4 – 7)

Gates are used to control access to entry points

within the target code segment The gate descrip-

tors are call gates task gates interrupt gates and

trap gates Gates provide a level of indirection be-

tween the source and destination of the control

transfer This indirection allows the CPU to automati-

cally perform protection checks and control entry

point of the destination Call gates are used to

change privilege levels (see Privilege) task gates

are used to perform a task switch and interrupt and

trap gates are used to specify interrupt service rou-

tines The interrupt gate disables interrupts (resets

IF) while the trap gate does not

Figure 13 shows the format of the gate descriptors

The descriptor contains a destination pointer that

points to the descriptor of the target segment and

the entry point offset The destination selector in an

interrupt gate trap gate and call gate must refer to a

code segment descriptor These gate descriptors

contain the entry point to prevent a program from

constructing and using an illegal entry point Task

gates may only refer to a task state segment Since

task gates invoke a task switch the destination off-

set is not used in the task gate

13

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