MT46V16M16FG データシートの表示（PDF） - Micron Technology
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MT46V16M16FG Datasheet PDF : 80 Pages
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Table 4: Burst Definition
STARTING
BURST COLUMN
LENGTH ADDRESS
ORDER OF ACCESSES
WITHIN A BURST
TYPE=
TYPE=
SEQUENTIAL INTERLEAVED
2
A0
0
0-1
0-1
1
1-0
1-0
4
A1 A0
00
0-1-2-3
0-1-2-3
01
1-2-3-0
1-0-3-2
10
2-3-0-1
2-3-0-1
11
3-0-1-2
3-2-1-0
8 A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
NOTE:
1. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
2. For a burst length of two, A1–Ai select the two-data-
element block; A0 selects the first access within the
block.
3. For a burst length of four, A2–Ai select the four-data-
element block; A0–A1 select the first access within the
block.
4. For a burst length of eight, A3–Ai select the eight-data-
element block; A0–A2 select the first access within the
block.
Read Latency
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 8.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 5,
CAS Latency (CL), on page 14 indicates the operating
frequencies at which each CAS latency setting can be
used.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
256Mb: x4, x8, x16
DDR SDRAM
CK#
CK
COMMAND
DQS
DQ
CK#
CK
COMMAND
DQS
DQ
Figure 8: CAS Latency
T0
T1
T2 T2n
T3 T3n
READ
NOP
NOP
NOP
CL = 2
T0
READ
T1
T2 T2n T3 T3n
NOP
NOP
NOP
CL = 2.5
Burst Length = 4 in the cases shown
Shown with nominal tAC, tDQSCK, and tDQSQ
TRANSITIONING DATA
DON’T CARE
Table 5: CAS Latency (CL)
SPEED
-6/-6R/-6T
-75E
-75Z
-75
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHz)
CL = 2
75 £ f £ 133
75 £ f £ 133
75 £ f £ 133
75 £ f £ 100
CL = 2.5
75 £ f £ 167
75 £ f £ 133
75 £ f £ 133
75 £ f £ 133
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7–A12
each set to zero, and bits A0–A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9–A12 each set
to zero, bit A8 set to one, and bits A0–A6 set to the
desired values. Although not required by the Micron
device, JEDEC specifications recommend when a
LOAD MODE REGISTER command is issued to reset
the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
09005aef8076894f
256MBDDRx4x8x16_2.fm - Rev. F 6/03 EN
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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