MT46V16M16FG データシートの表示（PDF） - Micron Technology

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MT46V16M16FG

256Mb: x4, x8, x16 DDR SDRAM

Micron Technology 

for each burst type in the Operation section of this

data sheet. The user must not issue another command

to the same bank until the precharge time (tRP) is

completed.

BURST TERMINATE

The BURST TERMINATE command is used to trun-

cate READ bursts (with auto precharge disabled). The

most recently registered READ command prior to the

BURST TERMINATE command will be truncated, as

shown in the Operation section of this data sheet. The

open page, which the READ burst was terminated

from, remains open.

AUTO REFRESH

AUTO REFRESH is used during normal operation of

the DDR SDRAM and is analogous to CAS#-BEFORE-

RAS# (CBR) refresh in FPM/EDO DRAMs. This com-

mand is nonpersistent, so it must be issued each time

a refresh is required. All banks must be idle before an

AUTO REFRESH command is issued.

The addressing is generated by the internal refresh

controller. This makes the address bits a “Don’t Care”

during an AUTO REFRESH command. The 256Mb

DDR SDRAM requires AUTO REFRESH cycles at an

average interval of 7.8125µs (maximum).

To allow for improved efficiency in scheduling and

switching between tasks, some flexibility in the abso-

lute refresh interval is provided. A maximum of eight

AUTO REFRESH commands can be posted to any

given DDR SDRAM, meaning that the maximum abso-

lute interval between any AUTO REFRESH command

and the next AUTO REFRESH command is 9 x 7.8125µs

(70.3µs). Note, the JEDEC specification only allows 8 x

7.8125µs, thus the Micron specification exceeds the

256Mb: x4, x8, x16

DDR SDRAM

JEDEC requirement by one clock. This maximum

absolute interval is to allow future support for DLL

updates internal to the DDR SDRAM to be restricted to

AUTO REFRESH cycles, without allowing excessive

drift in tAC between updates.

Although not a JEDEC requirement, to provide for

future functionalities, CKE must be active (HIGH) dur-

ing the auto refresh period. The auto refresh period

begins when the AUTO REFRESH command is regis-

tered and ends tRFC later.

SELF REFRESH

The SELF REFRESH command can be used to retain

data in the DDR SDRAM, even if the rest of the system

is powered down. When in the self refresh mode, the

DDR SDRAM retains data without external clocking.

The SELF REFRESH command is initiated like an

AUTO REFRESH command except CKE is disabled

(LOW). The DLL is automatically disabled upon enter-

ing SELF REFRESH and is automatically enabled upon

exiting SELF REFRESH. (A DLL reset and 200 clock

cycles must then occur before a READ command can

be issued.) Input signals except CKE are “Don’t Care”

during SELF REFRESH. VREF voltage is also required for

the full duration of the SELF REFRESH.

The procedure for exiting self refresh requires a

sequence of commands. First, CK and CK# must be

stable prior to CKE going back HIGH. Once CKE is

HIGH, the DDR SDRAM must have NOP commands

issued for tXSNR because time is required for the com-

pletion of any internal refresh in progress. A simple

algorithm for meeting both refresh and DLL require-

ments is to apply NOPs for tXSNR time, then a DLL

reset and NOPs for 200 additional clock cycles before

applying any other command.

09005aef8076894f

256MBDDRx4x8x16_2.fm - Rev. F 6/03 EN

18

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2003 Micron Technology, Inc.

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