MT46V16M16FG データシートの表示（PDF） - Micron Technology

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MT46V16M16FG

256Mb: x4, x8, x16 DDR SDRAM

Micron Technology 

All other combinations of values for A7–A12 are

reserved for future use and/or test modes. Test modes

and reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

Extended Mode Register

The extended mode register controls functions

beyond those controlled by the mode register; these

additional functions are DLL enable/disable and out-

put drive strength. These functions are controlled via

the bits shown in Figure 9. The extended mode register

is programmed via the LOAD MODE REGISTER com-

mand to the mode register (with BA0 = 1 and BA1 = 0)

and will retain the stored information until it is pro-

grammed again or the device loses power. The

enabling of the DLL should always be followed by a

LOAD MODE REGISTER command to the mode regis-

ter (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when

all banks are idle and no bursts are in progress, and the

controller must wait the specified time before initiat-

ing any subsequent operation. Violating either of these

requirements could result in unspecified operation.

Output Drive Strength

The normal drive strength for all outputs are speci-

fied to be SSTL_2, Class II. The x16 supports a pro-

grammable option for reduced drive. This option is

intended for the support of the lighter load and/or

point-to-point environments. The selection of the

reduced drive strength will alter the DQ pins and DQS

pins from SSTL_2, Class II drive strength to a reduced

drive strength, which is approximately 54 percent of

the SSTL_2, Class II drive strength.

256Mb: x4, x8, x16

DDR SDRAM

DLL Enable/Disable

When the part is running without the DLL enabled,

device functionality may be altered. The DLL must be

enabled for normal operation. DLL enable is required

during power-up initialization and upon returning to

normal operation after having disabled the DLL for the

purpose of debug or evaluation. (When the device

exits self refresh mode, the DLL is enabled automati-

cally.) Any time the DLL is enabled, 200 clock cycles

must occur before a READ command can be issued.

Figure 9: Extended Mode Register

Definition

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Extended Mode

01 11

Operating Mode

DS DLL Register (Ex)

E0

DLL

0

Enable

1

Disable

E12 Drive Strength

0

Normal

1

Reduced

E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E23

0 0 0 0 0 0 00 0 0 0

– – – – – – –– – – –

E1, E0

Valid

–

Operating Mode

Reserved

Reserved

NOTE:

1. E14 and E13 (BA1 and BA0) must be “0, 1” to select the

extended mode register vs. the base mode register.

2. The reduced drive strength option is not supported on

the x4 and x8 versions; it is only available on the x16

version.

3. The QFC# option is not supported.

09005aef8076894f

256MBDDRx4x8x16_2.fm - Rev. F 6/03 EN

15

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2003 Micron Technology, Inc.

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