M59DR032 データシートの表示（PDF） - STMicroelectronics

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M59DR032

32 Mbit (2Mb x16, Dual Bank, Page) 1.8V Supply Flash Memory

STMicroelectronics 

M59DR032A, M59DR032B

Table 20. CFI Query System Interface Information

Offset

Data

Description

VDD Logic Supply Minimum Program/Erase or Write voltage

1Bh

0017h

bit 7 to 4

BCD value in volts

bit 3 to 0

BCD value in 100 millivolts

VDD Logic Supply Maximum Program/Erase or Write voltage

1Ch

0022h

bit 7 to 4

BCD value in volts

bit 3 to 0

BCD value in 100 millivolts

VPP [Programming] Supply Minimum Program/Erase voltage

1Dh

0000h

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 millivolts

Note: This value must be 0000h if no VPP pin is present

VPP [Programming] Supply Maximum Program/Erase voltage

1Eh

00C0h

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 millivolts

Note: This value must be 0000h if no VPP pin is present

1Fh

0004h Typical timeout per single byte/word program (multi-byte program count = 1), 2n µs

(if supported; 0000h = not supported)

20h

0000h Typical timeout for maximum-size multi-byte program or page write, 2n µs

(if supported; 0000h = not supported)

21h

000Ah Typical timeout per individual block erase, 2n ms

(if supported; 0000h = not supported)

22h

0000h Typical timeout for full chip erase, 2n ms

(if supported; 0000h = not supported)

23h

0004h Maximum timeout for byte/word program, 2n times typical (offset 1Fh)

(0000h = not supported)

24h

0000h Maximum timeout for multi-byte program or page write, 2n times typical (offset 20h)

(0000h = not supported)

25h

0004h Maximum timeout per individual block erase, 2n times typical (offset 21h)

(0000h = not supported)

26h

0000h Maximum timeout for chip erase, 2n times typical (offset 22h)

(0000h = not supported)

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