TLIU04C1 データシートの表示（PDF） - Agere -> LSI Corporation

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TLIU04C1

Quad T1/E1 Line Interface

Agere -> LSI Corporation 

Advance Data Sheet, Rev. 2

April 1999

TLIU04C1 Quad T1/E1 Line Interface

Microprocessor Mode (continued)

Pin Information (continued)

Table 1. Pin Descriptions (continued)

Pin

Symbol Type*

Name/Description

138, 19, RPD/RDATA

66, 91

[1—4]

139, 18, RCLK/ALOS

67, 90

[1—4]

140, 17, TND[1—4]

68, 89

O Receive Positive Data. When in dual-rail (DUAL = 1: register 5, bit 4) clock

recovery mode (CDR = 1: register 5, bit 0), this signal is the received positive

NRZ data to the terminal equipment. When in data slicing mode (CDR = 0),

this signal is the raw sliced positive data of the front end.

Receive Data. When in single-rail (DUAL = 0: register 5, bit 4) clock recovery

mode (CDR = 1: register 5, bit 0), this signal is the received NRZ data.

O Receive Clock. In clock recovery mode (CDR = 1: register 5, bit 0), this

signal is the recovered receive clock for the terminal equipment. The duty

cycle of RCLK is 50% ± 5%.

Analog Loss of Signal. In data slicing mode (CDR = 0: register 5, bit 0), this

signal is asserted high to indicate low amplitude receive data at the RTIP/

RRING inputs.

I Transmit Negative Data. This signal is the transmit negative NRZ data from

the terminal equipment.

141, 16, TPD/TDATA

69, 88

[1—4]

142, 15,

70, 87

110

TCLK[1—4]

MPMODE

108

MPMUX

107

WR_DS

I Transmit Positive Data. When in dual-rail mode (DUAL = 1: register 5, bit 4),

this signal is the transmit positive NRZ data from the terminal equipment.

Transmit Data. When in single-rail mode (DUAL = 0: register 5, bit 4), this

signal is the transmit NRZ data from the terminal equipment.

I Transmit Clock. DS1 (1.544 MHz ± 32 ppm) or CEPT (2.048 MHz ±

50 ppm) clock signal from the terminal equipment.

I Microprocessor Mode. When MPMODE = 1, the device uses the address

latch enable type microprocessor read/write protocol with separate read and

write controls. Setting MPMODE = 0 allows the device to use the address

strobe type microprocessor read/write protocol with a separate data strobe

and a combined read/write control.

I Microprocessor Multiplex Mode. Setting MPMUX = 1 allows the

microprocessor interface to accept multiplexed address and data signals.

Setting MPMUX = 0 allows the microprocessor interface to accept

demultiplexed (separate) address and data signals.

I Write (Active-Low). If MPMODE = 1 (pin 110), this pin is asserted low by the

microprocessor to initiate a write cycle.

Data Strobe (Active-Low). If MPMODE = 0 (pin 21), this pin becomes the

data strobe for the microprocessor. When R/W = 0 (pin 111) initiating a write,

a low applied to this pin latches the signal on the data bus into internal

registers.

111

RD_R/W

I Read (Active-Low). If MPMODE = 1 (pin 110), this pin is asserted low by the

microprocessor to initiate a read cycle.

Read/Write. If MPMODE = 0 (pin 110), this pin is asserted high by the

microprocessor to initiate a read cycle or asserted low to initiate a write

cycle.

* I = input, O = output, Iu indicates an input with internal pull-up; Id indicates an input with internal pull-down, P = power. Resistance value of all

internal pull-ups or pull-downs is 50 kΩ, unless otherwise specified.

Lucent Technologies Inc.

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