IDT79R3500 データシートの表示（PDF） - Integrated Device Technology

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IDT79R3500

RISC CPU PROCESSOR RISCore™

Integrated Device Technology 

IDT79R3500 RISC CPU PROCESSOR RISCore

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT79R3500 PIPELINE ARCHITECTURE

The execution of a single IDT79R3500 integer instruction

consists of five pipe stages while floating point instruction

takes six pipe stages. They are:

1) IF—Instruction fetch. The processor calculates the

instruction address required to read from the I cache.

2) RD—The instruction is present on the data bus during

phase one of this pipe stage. Instruction decode occurs

during phase two. Operands are read from the registers if

required.

3) ALU—Perform the required operation on instruction

operands. If this is a FPA instruction, instruction execution

commences.

4) MEM—Access memory. If the instruction is a load or

store, the data is presented or captured during phase 2 of

this pipe stage.

5) WB—Write integer results back into register file. In

FPA cycles this pipe stage is used for exceptions.

6) FWB—The FPA uses this stage to write back ALU

results to its register file.

Each of these steps requires approximately one FPA cycle

as shown in Figure 10. (parts of some operations spill over into

another cycle while other operations require only 1/2 cycle.)

The CPU uses a five stage pipeline while while the FPA

uses a 6 stage to achieve an instruction execution rate

approaching one instruction per cycle. Thus, execution of six

instructions at a time are overlapped as shown in Figure 11.

This pipeline operates efficiently because different CPU

resources (address and data bus accesses, ALU operations,

register accesses, and so on) are utilized on a non-interfering

basis.

MEMORY SYSTEM HIERARCHY

The high performance capabilities of the IDT79R3500

processor demand system configurations incorporating tech-

niques frequently employed in large, mainframe computers

but seldom encountered in systems based on more traditional

microprocessors.

A primary goal of systems employing RISC techniques is to

minimize the average number of cycles each instruction

requires for execution. Techniques to reduce cycles-per-

instruction include a compact and uniform instruction set, a

deep instruction pipeline (as described above), and utilization

of optimizing compilers. Many of the advantages obtained

from these techniques can, however, be negated by an

inefficient memory system.

Figure 12 illustrates memory in a simple microprocessor

system. In this system, the CPU outputs addresses to memory

and reads instructions and data from memory or writes data to

memory. The address space is completely undifferentiated:

instructions, data, and I/O devices are all treated the same. In

such a system, a primary limiting performance factor is memory

bandwidth.

Microprocessor

(CPU)

Data

Address

Memory

(and I/O)

2871 drw 12

Figure 12. A Simple Microprocessor Memory System

Figure 13 illustrates a memory system that supports the

significantly greater memory bandwidth required to take full

advantage of the IDT79R3500’s performance capabilities.

The key features of this system are:

Data

IDT79R3500A

Microprocessor

Address

Instruction

Cache

Data

Cache

Write

Buffer

Data

Main Memory

Address

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Figure 13. An IDT79R3500 System with a

High-Performance Memory System

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