IDT79R3500 データシートの表示（PDF） - Integrated Device Technology

部品番号

コンポーネント説明

メーカー

IDT79R3500

RISC CPU PROCESSOR RISCore™

Integrated Device Technology 

IDT79R3500 RISC CPU PROCESSOR RISCore

MILITARY AND COMMERCIAL TEMPERATURE RANGES

General Purpose Registers

(FGR/FPR)

63

32 31

0

FGR1

FGR3

FGR0

FGR2

Control/Status Register

31

0

FGR5

FGR4

Exceptions/Enables/Modes

FGR27

FGR29

FGR31

FGR26

FGR28

FGR30

Implementation/Revision

31

Register

0

2871 drw 03

Figure 3. FPA Registers

Instruction Set Overview

All IDT79R3500 instructions are 32 bits long, and there

are only three instruction formats. This approach simplifies

instruction decoding, thus minimizing instruction execution

time. The IDT79R3500 processor initiates a new instruction

on every run cycle, and is able to complete an instruction on

almost every clock cycle. The only exceptions are the Load

instructions and Branch instructions, which each have a single

cycle of latency associated with their execution. Note, how-

ever, that in the majority of cases the compilers are able to fill

these latency cycles with useful instructions which do not

require the result of the previous instruction. This effectively

eliminates these latency effects.

The actual instruction set of the CPU was determined after

extensive simulations to determine which instructions should

be implemented in hardware, and which operations are best

synthesized in software from other basic instructions. This

methodology resulted in the IDT79R3500 having the highest

performance of any available microprocessor.

I-Type (Immediate)

31 26 25 21 20 16 15

0

op

rs

rt

immediate

J-Type (Jump)

31 26 25

0

op

target

R-Type (Register)

31 26 25 21 20 16 15 11 10 6 5 0

op

rs

rt

rd

re funct

2871 drw 04

Figure 4. IDT79R3500 Instruction Formats

The IDT79R3500 instruction set can be divided into the

following groups:

• Load/Store instructions move data between memory and

general registers. They are all I-type instructions, since the

only addressing mode supported is base register plus 16-

bit, signed immediate offset.

The Load instruction has a single cycle of latency, which

means that the data being loaded is not available to the

instruction immediately after the load instruction. The

compiler will fill this delay slot with either an instruction

which is not dependent on the loaded data, or with a NOP

instruction. There is no latency associated with the store

instruction.

Loads and Stores can be performed on byte, half-word,

word, or unaligned word data (32-bit data not aligned on a

modulo-4 address). The CPU cache is constructed as a

write-through cache.

• Computational instructions perform arithmetic, logical

and shift operations on values in registers. They occur in

both R-type (both operands and the result are registers)

and I-type (one operand is a 16-bit immediate) formats. FP

computational instructions perform arithmetic operations

on floating point values in the FPA registers. Note that

computational instructions are three operand instructions;

that is, the result of the operation can be stored into a

different register than either of the two operands. This

means that operands need not be overwritten by arithmetic

operations. This results in a more efficient use of the large

register set.

• Conversion instructions perform conversion operations

on the floating point values in the FPA registers.

• Compare intructions perform comparisons of the contents

of FPA registers and set a condition bit based on the

results. The result of the compare operations is tied

directly to Cp Cond (1) for software testing.

• Jump and Branch instructions change the control flow of

a program. Jumps are always to a paged absolute address

formed by combining a 26-bit target with four bits of the

Program counter (J-type format, for subroutine calls), or

32-bit register byte addresses (R-type, for returns and

Share Link: