IDT79R3500 データシートの表示（PDF） - Integrated Device Technology

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IDT79R3500

RISC CPU PROCESSOR RISCore™

Integrated Device Technology 

IDT79R3500 RISC CPU PROCESSOR RISCore

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Operating Modes

The IDT79R3500 has two operating modes: User mode

and Kernel mode. The IDT79R3500 normally operates in the

User mode until an exception is detected forcing it into the

Kernel mode. It remains in the Kernel mode until a Restore

From Exception (RFE) instruction is executed. The manner in

which memory addresses are translated or mapped depends

on the operating mode of the IDT79R3500. Figure 7 shows the

MMU translation performed for each of the operating modes.

User Mode—in this mode, a single, uniform virtual address

space (kuseg) of 2GB is available. When the TLB is used,

each virtual address is extended with a 6-bit process identifier

field to form unique virtual addresses. All references to this

segment are mapped through the TLB. Use of the cache for

up to 64 processes is determined by bit settings for each page

within the TLB entries. If the TLB is not used, these addresses

are translated to begin at 1GB of the physical address space.

Kernel Mode—four separate segments are defined in this

mode:

• kuseg—when in the kernel mode, references to this seg-

ment are treated just like user mode references, thus

streamlining kernel access to user data.

• kseg0—references to this 512MB segment use cache

memory but are not mapped through the TLB. Instead,

they always map to the first 0.5GB of physical address

space.

• kseg1—references to this 512MB segment are not mapped

through the TLB and do not use the cache. Instead, they

are hard-mapped into the same 0.5GB segment of physi-

cal address space as kseg0.

• kseg2—when the TLB is not used, references to this 1GB

segment directly addresses the upper 1GB of physical

address space. These addresses are defined to be kernel

mode which are cacheable. When the TLB is used, refer-

ences to this 1GB segment are always mapped through

the TLB and use of the cache is determined by bit settings

within the TLB entry.

FPA COPROCESSOR OPERATION (CP1)

The FPA continually monitors the processor instruction

stream. If an instruction does not apply to the coprocessor, it

is ignored; if an instruction does apply to the coprocessor, the

FPA executes that instruction and transfers necessary result

and exception data synchronously to the main processor.

The FPA performs three types of operations:

• Loads and Stores;

• Moves;

• Two- and three-register floating-point operations.

Load, Store, and Move Operation

Load, Store, and Move operations data between memory

or the integer registers and the FPA registers. These opera-

tions perform no format conversions and cause no floating-

point exceptions. Load, Store, and Move operations reference

a single 32-bit word of either the Floating-Point General

Registers (FGR) or the Floating-Point Control Registers (FCR).

Floating-Point Operations

The FPA supports the following single- and double-preci-

sion format floating-point operations:

• Add

• Subtract

• Multiply

• Divide

• Absolute Value

• Move

• Negate

• Compare

In addition, the FPA supports conversions between single-

and double-precision floating-point formats and fixed-point

formats.

The FPA incorporates separate Add/Subtract, Multiply,

and Divide units, each capable of independent and concurrent

operation. Thus, to achieve very high performance, floating

point divides can be overlapped with floating point multiplies

and floating point additions. These floating point operations

occur independently of the actions of the CPU, allowing

further overlap of integer and floating point operations. Figure

9 illustrates an example of the types of overlap permissible.

Exceptions

The FPA supports all five IEEE standard exceptions:

• Invalid Operation

• Inexact Operation

• Division by Zero

• Overflow

• Underflow

The FPA also suppoerts the optional, Unimplemented

Operation exception that allows unimplemented instructions

to trap to software emulation routines.

The FPA provides precise exception capability to the CPU;

that is, the execution of a floating point operation which

generates an exception causes that exception to occur at the

CPU instruction which caused the operation. This precise

exception capability is a requirement in applications and

languages which provide a mechanism for local software

exception handlers within software modules.

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