IDT79R3500 データシートの表示（PDF） - Integrated Device Technology

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IDT79R3500

RISC CPU PROCESSOR RISCore™

Integrated Device Technology 

IDT79R3500 RISC CPU PROCESSOR RISCore

MILITARY AND COMMERCIAL TEMPERATURE RANGES

0

2

4

6

8

10

12

DIV.S

MUL.S

ADD

STORE (SWC1)

NON FPU

MUL.S

Only Load, Store, and Move operations

are permitted in FPA during these cycles.

Other FPA instructions can proceed during

these cycles. However, two multiply or two

divide operation cannot be overlapped.

These cycles are free for integer operations

in the CPU.

ADD.S

STORE (SWC1)

LOAD (LWC1)

STORE (SWC1)

NON FPU

Figure 9. Examples of Overlapping Floating Point Operation

IF

RD

ALU

I-Cache

RF

OP

MEM

D-Cache

WB

Register file write

back or FP

exceptions

2871 drw 09

FWB

*FpWB

One Cycle

Figure 10. Instruction Execution

* FP ops only

2871 drw 10

IF

RD

IF

Instruction

Flow

ALU

MEM

WB

*FWB

RD

ALU

MEM

WB

*FWB

IF

RD

ALU

MEM

WB

*FWB

IF

RD

ALU

MEM

WB

*FWB

IF

RD

ALU

MEM

WB

*FWB

IF

RD

ALU

MEM

WB

*FWB

Current

CPU

Cycle

Figure 11. IDT79R3500 Execution Sequence

2871 drw 11

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