CS61583 データシートの表示（PDF） - Cirrus Logic

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CS61583

Dual T1/E1 Line Interface

Cirrus Logic 

CS61583

JTAG Instructions and Instruction Register (IR)

The instruction register (2 bits) allows the in-

struction to be shifted into the JTAG circuit. The

instruction selects the test to be performed or the

data register to be accessed or both. The valid

instructions are shifted in LSB first and are listed

below:

IR CODE

00

01

10

11

INSTRUCTION

EXTEST

SAMPLE/PRELOAD

IDCODE

BYPASS

EXTEST Instruction: The EXTEST instruction

allows testing of off-chip circuitry and board-

level interconnect. EXTEST connects the BSR to

the J-TDI and J-TDO pins. The normal path be-

tween the CS61583 logic and I/O pins is broken.

The signals on the output pins are loaded from

the BSR and the signals on the input pins are

loaded into the BSR.

SAMPLE/PRELOAD Instruction: The SAM-

PLE/PRELOAD instructions allows scanning of

the boundary-scan register without interfering

with the operation of the CS61583. This instruc-

tion connects the BSR to the J-TDI and J-TDO

pins. The normal path between the CS61583

logic and its I/O pins is maintained. The signals

on the I/O pins are loaded into the BSR. Addi-

tionally, this instruction can be used to latch

values into the digital output pins.

IDCODE Instruction: The IDCODE instruction

connects the device identification register to the

J-TDO pin. The IDCODE instruction is forced

into the instruction register during the Test-

Logic-Reset controller state.The default

instruction is IDCODE after a device reset.

BYPASS Instruction: The BYPASS instruction

connects the minimum length bypass register be-

tween the J-TDI and J-TDO pins and allows data

to be shifted in the Shift-DR controller state.

Internal Testing Considerations

Note that the INTEST instruction is not sup-

ported because of the difficulty in performing

significant internal tests using JTAG.

The one test that could be easily performed us-

ing an arbitrary clock rate on TCLK and

REFCLK is a local loopback with jitter attenu-

ator disabled. However, this test provides limited

fault coverage and is only useful in determining

if the device had been catastrophically destroyed.

Alternatively, catastrophic destruction of the de-

vice and/or surrounding board traces can be

detected using EXTEST. Therefore, the INTEST

instruction provides limited testing capability

and was not included in the CS61583.

JTAG TAP Controller

Figure 12 shows the state diagram for the TAP

state machine. A description of each state fol-

lows. Note that the figure contains two main

branches to access either the data or instruction

registers. The value shown next to each state

transition in this figure is the value present at

J-TMS at each rising edge of J-TCK.

Test-Logic-Reset State

In this state, the test logic is disabled to continue

normal operation of the device. During initiali-

zation, the CS61583 initializes the instruction

register with the IDCODE instruction.

Regardless of the original state of the controller,

the controller enters the Test-Logic-Reset state

when the J-TMS input is held high for at least

five rising edges of J-TCK. The controller re-

mains in this state while J-TMS is high. The

CS61583 processor automatically enters this

state at power-up.

Run-Test/Idle State

This is a controller state between scan opera-

tions. Once in this state, the controller remains

in the state as long as J-TMS is held low. The

DS172PP5

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