MT28S4M16B1LLFG-10 データシートの表示（PDF） - Micron Technology
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MT28S4M16B1LLFG-10 Datasheet PDF : 58 Pages
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COMMANDS
Truth Table 1 provides a quick reference of avail-
able commands for SDRAM-compatible operation. This
is followed by a written description of each command.
Additional truth tables appear later.
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
TRUTH TABLE 1
SDRAM-COMPATIBLE INTERFACE COMMANDS AND DQM OPERATION
(Notes: 1)
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank, column and start READ burst)
WRITE (Select bank, column and start WRITE)
BURST TERMINATE
ACTIVE TERMINATE
LOAD COMMAND REGISTER
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
CS# RAS# CAS# WE# DQM ADDR DQs NOTES
HXXXX
X
X
L HHHX
X
X
L L H H X Bank/Row X
2
L H L H X Bank/Col X
3
L H L L X Bank/Col Valid 3, 4
L HHL X
X
Active
L LHLX
X
X
5
L
L
L H X Com-Code X
6, 7
L L L L X Op-Code X
8
––––L
–
Active 9
– – – –H
–
High-Z 9
NOTE:
1. CKE is HIGH for all commands shown.
2. x32: A0–A10, x16: A0–A11 provide row address, and BA0 and BA1 determine which bank is made active.
3. A0–A7 provide column address, and BA0 and BA1 determine which bank is being read from or written to.
4. A PROGRAM SETUP command sequence (see Truth Table 2a) must be completed prior to executing a WRITE.
5. ACTIVE TERMINATE is functionally equivalent to the SDRAM PRECHARGE command; however, PRECHARGE (deactivate row
in bank or banks) is not required for SyncFlash memory.
A10 LOW: BA0 and BA1 determine the bank to be active terminated.
A10 HIGH: All banks are active terminated and BA0 and BA1 are “Don’t Care.”
6. A0–A7 define the com-code, and A8–A11 are “Don’t Care” for this operation. See Truth Table 2a.
7. LOAD COMMAND REGISTER (LCR) replaces the SDRAM auto refresh or self refresh mode, which is not required for
SyncFlash memory. LCR is the first cycle for Flash memory hardware command sequences (HCS). See Truth Table 2a.
After the hardware LCR function is disabled, SyncFlash will treat SDRAM REFRESH or AUTO REFRESH commands as NOPs.
A software command sequence (SCS) is available to perform all operations described in Truth Table 2b.
8. A0–A10 define the op-code written to the mode register. The mode register can be dynamically loaded each cycle,
provided tMRD is satisfied. The default mode register value is stored in the nvmode register. The contents of the
nvmode register are automatically loaded into the mode register during device initialization.
9. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
64Mb: x16, x32 SyncFlash
MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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