MT28S4M16B1LLFG-10 データシートの表示（PDF） - Micron Technology

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MT28S4M16B1LLFG-10

SYNCFLASH® MEMORY

Micron Technology 

Operation

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be is-

sued to a bank within the SyncFlash memory, a row in

that bank must be “opened.” (Note: A row will not be

activated for LCR/active/read or LCR/active/write com-

mand sequences. See Flash Memory Architecture sec-

tion for additional information). This is accomplished

via the ACTIVE command, which selects both the bank

and the row to be activated.

After opening a row (issuing an ACTIVE command),

a READ or WRITE command may be issued to that row,

subject to the tRCD specification. tRCD (MIN) should

be divided by the clock period and rounded up to the

next whole number to determine the earliest clock edge

after the ACTIVE command on which a READ or WRITE

command can be entered. For example, a tRCD specifi-

cation of 20ns with a 125 MHz clock (8ns period) results

in 2.5 clocks rounded to 3. This is reflected in Figure 4,

which covers any case where 2 < tRCD (MIN)/tCK £ 3.

(The same procedure is used to convert other specifi-

cation limits from time units to clock cycles).

A subsequent ACTIVE command to a different row

in the same bank can be issued without having t o close

a previous active row, provided the minimum time in-

terval between successive ACTIVE commands to the

same bank is defined by tRC.

A subsequent ACTIVE command to another bank

can be issued while the first bank is being accessed,

which results in a reduction of total row access over-

head. The minimum time interval between successive

ACTIVE commands to different banks is defined by

tRRD.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

Figure 3

Activating a Specific Row in a

Specific Bank

CLK

CKE HIGH

CS#

RAS#

CAS#

WE#

x32: A0–A10

x16: A0–A11

BA0,BA1

ROW

ADDRESS

BANK

ADDRESS

Figure 4

Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK £ 3

T0

T1

T2

T3

T4

CLK

COMMAND

ACTIVE

NOP

NOP

READ or WRITE

tRCD

DON’T CARE

64Mb: x16, x32 SyncFlash

MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02

18

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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