ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
TRUTH TABLE 2b – SOFTWARE COMMAND SEQUENCES (SCS)
(Notes: 1, 2, 4, 5; see notes on page 16)
OPERATION
FIRST
CYCLE
READ DEVICE CONFIGURATION10
Command
Active
ADDR
=
88h
Bank Address =
X
DQ
=
X
RP#
=
H
READ STATUS REGISTER
Command
Active
ADDR =
88h
Bank Address =
X
DQ =
X
RP# =
H
CLEAR STATUS REGISTER
Command
Active
ADDR =
88h
Bank Address =
X
DQ =
X
RP# =
H
ERASE SETUP/CONFIRM
Command
Active
ADDR =
X
Bank Address =
X
DQ =
X
RP# =
H
PROGRAM SETUP/CONFIRM
Command
Active
ADDR =
X
Bank Address =
X
DQ =
X
RP#9 =
H
PROTECT BLOCK/CONFIRM
Command
Active
ADDR =
X
Bank Address =
X
DQ =
X
RP#9 =
H
PROTECT DEVICE CONFIRM
Command
Active
ADDR =
X
Bank Address =
X
DQ =
X
RP#9 =
H
SECOND
CYCLE
Write
90h
X
X
H
Write
70h
X
X
H
Write
50h
X
X
H
Write
55h
Bank12
X
H
Write
55h
Bank12
X
H
Write
55h
Bank12
X
H
Write
55h
Bank12
X
H
THIRD
CYCLE
Active
CAROW
Bank12
X
H
Active
X
X
X
H
Active
55h
Bank12
X
H
Active
55h
Bank12
X
H
Active
55h
Bank12
X
H
Active
55h
Bank12
X
H
FOURTH
CYCLE
Read
CACOL
Bank12
X
H
Read
X
X
X
H
Write
2Ah
Bank12
55h
H
Write
2Ah
Bank12
55h
H
Write
2Ah
Bank12
55
H
Write
2Ah
Bank12
55h
H
FIFTH
CYCLE
Active
80h
Bank12
X
H
Active
80h
Bank12
X
H
Active
80h
Bank12
X
H
Active
80h
Bank12
X
H
(continued on next page)
SIXTH
CYCLE
SEVENTH
CYCLE
EIGHTH
CYCLE
Write
20h
Bank12
A0h
H
Write
40h
Bank12
A0h
H
Write
60h
Bank12
A0h
H
Write
60h
Bank12
A0h
H
Active
Row
Bank12
X
H
Write
X
Bank12
D0h
H/VHH
Active
Row
Bank12
X
H
Write
Col
Bank12
DIN
H/VHH15
Active
Row11
Bank12
X
H
Write
X
Bank12
LBDa(IN)16
H/VHH15
Active
X10
Bank12
X
H
Write
X
Bank12
LBDa(IN)16
VHH
64Mb: x16, x32 SyncFlash
MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02
14
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©2002, Micron Technology, Inc.