MT28S4M16B1LLFG-10 データシートの表示（PDF） - Micron Technology

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MT28S4M16B1LLFG-10

SYNCFLASH® MEMORY

Micron Technology 

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new

commands from being executed by the SyncFlash

memory, regardless of whether the CLK signal is en-

abled. The SyncFlash memory is effectively deselected.

Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to

perform a NOP to a SyncFlash memory that is selected

(CS# is LOW). This prevents unwanted commands from

being registered during idle or wait states. Operations

already in progress are not affected.

LOAD MODE REGISTER

The mode register is loaded via inputs A0–A10. See

the mode register heading in the Register Definition

section. The LOAD MODE REGISTER command can

only be issued when all banks are idle, and a subse-

quent executable command cannot be issued until

tMRD is met. The data in the nvmode register is auto-

matically loaded into the mode register upon power-

up initialization and is the default mode setting unless

dynamically changed with the LOAD MODE REGIS-

TER command.

ACTIVE

The ACTIVE command is used to open (or activate)

a row in a particular bank for a subsequent access. The

value on the BA0, BA1 inputs selects the bank, and the

address provided on inputs (x32: A0–A10, x16: A0–A11)

selects the row. This row remains active for accesses

until the next ACTIVE command, power-down or reset.

READ

The READ command is used to initiate a burst read

access to an active row. The value on the BA0, BA1

inputs selects the bank, and the address provided on

inputs A0–A7 selects the starting column location. Read

data appears on the DQs subject to the logic level on

the DQM input two clocks earlier. If a given DQM signal

was registered HIGH, the corresponding DQs will be

High-Z two clocks later; if the DQM signal was regis-

tered LOW, the DQs will provide valid data.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

WRITE

The WRITE command is used to initiate a burst write

access. A WRITE command must be preceded by LCR/

ACTIVE. The value on the BA0, BA1 inputs selects the

bank, and the address provided on inputs A0–A7 se-

lects the column location.

Input data appearing on the DQs is written to the

memory array, subject to the DQM input logic level

appearing coincident with the data. If a given DQM

signal is registered LOW, the corresponding data will

be written to memory; if the DQM signal is registered

HIGH, the corresponding data inputs will be ignored,

and a WRITE will not be executed to that word/column

location. A WRITE command with DQM HIGH is con-

sidered a NOP.

ACTIVE TERMINATE

ACTIVE TERMINATE, which replaces the SDRAM

PRECHARGE command, is not required for SyncFlash

memory, but is functionally equivalent to the SDRAM

PRECHARGE command. ACTIVE TERMINATE can be

issued to terminate a BURST READ in progress and

may or may not be bank specific.

BURST TERMINATE

The BURST TERMINATE command is used to trun-

cate either fixed-length or full-page bursts. The most

recently registered READ or WRITE command prior to

the BURST TERMINATE command will be truncated as

shown in the Operation section of this data sheet.

BURST TERMINATE is not bank specific.

LOAD COMMAND REGISTER (HCS ONLY)

The LOAD COMMAND REGISTER command in the

HCS is used to initiate Flash memory control commands

to the command execution logic (CEL). The CEL re-

ceives and interprets commands to the device. These

commands control the operation of the internal state

machine and the read path (i.e., memory array, ID reg-

ister or status register). However, there are restrictions

on what commands are allowed in this condition. See

the Command Execution section of Flash Memory Func-

tional Description for more details.

64Mb: x16, x32 SyncFlash

MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02

17

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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