M29W400 データシートの表示（PDF） - STMicroelectronics
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コンポーネント説明
メーカー
M29W400
STMicroelectronics
M29W400 Datasheet PDF : 34 Pages
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M29W400T, M29W400B
Table 15B. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W400T / M29W400B
Symbol Alt
Parameter
-120
VCC = 2.7V to 3.6V
Min
Max
-150
VCC = 2.7V to 3.6V
Min
Max
tAVAV
tWC Address Valid to Next Address Valid
120
150
tELWL
tCS Chip Enable Low to Write Enable Low
0
0
tWLWH
tWP Write Enable Low to Write Enable High
50
65
tDVWH
tDS Input Valid to Write Enable High
50
65
tWHDX
tDH Write Enable High to Input Transition
0
0
tWHEH
tCH Write Enable High to Chip Enable High
0
0
tWHWL tWPH Write Enable High to Write Enable Low
30
35
tAVWL
tAS Address Valid to Write Enable Low
0
0
tWLAX
tAH Write Enable Low to Address Transition
50
65
tGHWL
Output Enable High to Write Enable Low
0
0
tVCHEL tVCS VCC High to Chip Enable Low
50
50
tWHGL
tOEH Write Enable High to Output Enable Low
0
0
tPHPHH (1,2) tVIDR RP Rise Time to VID
500
500
tPLPX
tWHRL (1)
tPHWL (1)
tRP RP Pulse Width
tBUSY Program Erase Valid to RB Delay
tRSP RP High to Write Enable Low
500
500
90
90
4
4
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
µs
Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address AAAAh
in the Byte-wide configuration or address 5555h in
the Word-wide configurationon third cycle after the
two Coded cycles. The Block Erase Confirm com-
mand 30h is similarly written on the sixth cycle after
another two Coded cycles. During the input of the
second command an address within the blockto be
erased is given and latched into the memory. Addi-
tional block Erase Confirm commands and block
addresses can be written subsequently to erase
other blocks in parallel, without further Coded cy-
cles. The erase will start after the erase timeout
period (see Erase Timer Bit DQ3 description).
Thus, additional Erase Confirm commands for
other blocks must be given within this delay. The
input of a new Erase Confirm command will restart
the timeout period. The status of the internal timer
can be monitored through the level of DQ3, if DQ3
is ’0’ the Block Erase Command has been given
and the timeout is running, if DQ3 is ’1’, the timeout
has expired and the P/E.C. is erasing the Block(s).
If the second command given is not an erase
confirm or if the Coded cycles are wrong, the
instruction aborts, and the device is reset to Read
Array. It is not necessary to program the block with
00h as the P/E.C. will do this automatically before
to erasing to FFh. Read operations after the sixth
rising edge of W or E output the status register
status bits.
18/34
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