M7040N データシートの表示（PDF） - STMicroelectronics
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M7040N Datasheet PDF : 159 Pages
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M7040N
Comparand Registers
The device contains 32 72-bit comparand regis-
ters (16 pairs) dynamically selected in every
SEARCH operation to store the comparand pre-
sented on the DQ Bus. The LEARN command will
later use these registers when executed. The
M7040N stores the SEARCH command’s Cycle A
comparand in the even-numbered register and the
Cycle B comparand in the odd-numbered register,
as shown in Figure 13.
Figure 13. Comparand Register Selection
During SEARCH and LEARN
Instructions
72
A ddr e ss
Index 143
0
0
1
2
4
6
72
0
1
3
5
7
15
30
31
AI04667
Mask Registers
The device contains 32 72-bit global mask regis-
ters (16 pairs) dynamically selected in every
SEARCH operation to select the search subfield.
The addressing of these registers is explained in
Figure 14. The four-bit GMR Index supplied on the
command (CMD) bus can apply 16 pairs of global
masks during the SEARCH and WRITE opera-
tions, as shown below.
Note: In 72-bit SEARCH and WRITE operations,
the host ASIC must program both the even and
odd mask registers with the same values.
Each mask bit in the GMRs is used during
SEARCH and WRITE operations. In SEARCH op-
erations, setting the mask bit to '1' enables com-
pares; setting the mask bit to '0' disables
compares (forced match) at the corresponding bit
position. In WRITE operations to the data or mask
array, setting the mask bit to '1' enables WRITEs;
setting the mask bit to '0' disables WRITEs at the
corresponding bit position.
Figure 14. Addressing the Global Masks
Register Array
72
A ddr e ss
Index 143
0
0
1
2
2
4
3
6
4
8
5
10
6
12
7
14
8
16
9
18
10
20
11
22
12
24
13
26
14
28
15
30
72
0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
SEARCH and WRITE Command
Global Mask Selection
AI04668
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