M7040N データシートの表示（PDF） - STMicroelectronics
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M7040N Datasheet PDF : 159 Pages
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M7040N
The Read Burst Address Register (RBURREG)
These READ burst address register fields must be
programmed before burst read.
Table 13. Read Burst Register Description
Field
Range
Initial Value
Description
ADR
[15:0]
Address. This is the starting address of the data array or mask array
during a burst READ operation. It automatically increments by 1 for
0
each successive read of the data array or mask array. Once the
operation is complete, the contents of this field must be reinitialized
for the next operation.
[18:16]
Reserved.
BLEN
[27:19]
Length of Burst Access. The device is capable of writing from 4 up
0
to 511 locations in a single burst. The BLEN decrements
automatically. Once the operation is complete, the contents of this
field must be reinitialized for the next operation.
[71:28]
Reserved.
The Write Burst Address Register (WBURREG)
These WRITE burst address register fields must
be programmed before burst write.
Table 14. Write Burst Register Description
Field
Range
Initial Value
Description
ADR
[15:0]
Address. This is the starting address of the data array or mask array
during a burst WRITE operation. It automatically increments by 1 for
0
each successive write of the data array or mask array. Once the
operation is complete, the contents of this field must be reinitialized for
the next operation.
[18:16]
Reserved.
BLEN
[27:19]
Length of Burst Access. The device is capable of writing from 4 up
0
to 511 locations in a single burst. The BLEN decrements
automatically. Once the operation is complete, the contents of this
field must be reinitialized for the next operation.
[71:28]
Reserved.
The NFA Register
Bit [0] of each 72-bit data entry is a special bit des-
ignated for use in the operation of the LEARN
command. In 72-bit quadrants, the bit[0] indicates
whether a location is full (bit set to '1') or empty (bit
set to '0'). Every WRITE/LEARN command loads
the address of first 72-bit location that contains a
'0' in the entry’s bit[0]. This is stored in the NFA
register (see Table 15). If all the bits in a device are
set to '1,' the M7040N asserts FULO[1:0] to '1.'
In 144-bit-configured quadrants, the LSB of this
register is always set to '0.' The host ASIC must
set bit '0' and bit 72 in a 144-bit word to either '0' or
'1' to indicate full/empty status.
Note: Both bits (0 and 72) must be set to '0' or '1'
(e.g., '10' or '01' settings are invalid).
Table 15. NFA Register
Address
71 - 16
60
Reserved
15 - 0
Index
27/159
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